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path: root/arch/arm/plat-mxc
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2012-02-23ENGR00175222-1 IPUv3 pdev:Check fb size before reserve ov fbLiu Ying
This patch checks overlay fb size before reserve fb mem for it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit b29df373e547c83f9b3bcfd9a98016f462fa9ec2)
2012-02-15ENGR00174106-1 - EPDC fb: Support EPDC on MX 6DL/SDanny Nold
- Added EPDC and EPD PMIC (Maxim 17135) to MX6Q ARM2 board file - Added EPDC-related IOMUX and GPIO settings - Added EPDC clock configuration settings to clock file - Updated config files with EPDC and Maxim 17135 config entries Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-02-15ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.Fugang Duan
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: TO1.1 IEEE 1588 is convergent in Sabrelite board. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-14ENGR00174299-2: MSL part: add ePxP V2 driverRobby Cai
MSL part for ePxP v2 driver Signed-off-by: Robby Cai <R63905@freescale.com>
2012-02-13ENGR00174301 [mx6dl perfmon]add workaround for TKT055916Tony Lin
bit16 of GPR11 must be set to enable performance monitor Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-10ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1Tony Lin
remove the workaround For TO1.0: bit16 of GPR11 must be set to enable perfmon For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon. set 1/0 to enable/disable perfmon add workaround for mx6dl Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-10ENGR00173463 i.mx6dl: vpu: disable iram usageSammy He
Disable vpu iram since mx6dl platform iram isn't enough for vpu after VDOA/audio used it. Signed-off-by: Sammy He <r62914@freescale.com>
2012-02-10ENGR00174033-1 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-09ENGR00174037-1 Add HSIC suspend/resume featureTony LIU
MSL part - For HSIC, not connect nor disconnect, then WKCN, WKDC must not be set during suspend - For HSIC, must set bit 21 in host control registry after device connected to host controller - USB PHY 480M clock output must turn on to avoid about 10ms delay before sending out resume signal - HW_ANA_MISC clkgate delay must be set to 2 or 3 to avoid 24M OSCI not stable issue Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-02-08ENGR00172342-1 EDID parse audio data blocksAlan Tull
Add functionality to parse Audio Data Blocks from EDID data to find out what modes of LPCM are suppored by the HDMI sink device. The parsed settings are saved in the hdmi mfd. The HDMI audio driver will check the settings when the audio stream is opened and will then apply appropriate constraints. If we are unable to read from the EDID, then we default to supporting Basic Audio as defined by the HDMI specification (stereo, 16 bit, 32KHz, 44.1KHz, 48KHz PCM). Signed-off-by: Alan Tull <r80115@freescale.com>
2012-02-08ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.Fugang Duan
- Fix GPIO_16 IOMUX config. - Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: Enet work fine at 100/1000Mbps in TO1.1. IEEE 1588 timestamp is convergent. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-07ENGR00173869-8: i.mx6: ARM2: add i.mx6dl supportJason Liu
i.mx6dl and i.mx6q share the same ARM2 board due to the pin-pin compatible between them. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-7: i.mx6: sdma: add i.mx6dl supportJason Liu
add i.mx6dl support for sdma Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-6: i.mx6: gpio: add the i.mx6dl supportJason Liu
add the i.mx6dl support for gpio Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-4: i.mx6: add the i.mx6dl iomux supportJason Liu
externally, i.mx6dl is pin-pin compatible with i.mx6dq internally, i.mx6dl is totally different with iomux setting Checkpatch will throw some warnings in iomux-mx6dl.h file as: WARNING: line over 80 characters But for the readable, I intend not to fix these warnings, and linux upstream also has so many such kind of cases Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() supportJason Liu
In order to support one image for i.mx6q and i.mx6dl, we introduce the below functions by diff the value reading from ANATOP ID register. cpu_is_mx6q() and cpu_is_mx6dl() The layout for the register defines: Major Minor i.MX6Q1.1: 6300 01 i.MX6Q1.0: 6300 00 i.MX6DL1.0: 6100 00 For the common bits shared across all i.mx6 ports, we can use: cpu_is_mx6() for it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-2: i.mx6: add the i.mx6dl memory map and irq definionJason Liu
i.mx6dl shares with almost the same memory layout with i.mx6d/q except it adds some new fetures such as pxp/epdc etc. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-1: i.mx6: cosmetic the codeJason Liu
This is the cosmetic patch for the i.mx6 and make the prepartion for the coming i.mx6dl support. Why cosmetic? It's due to the code is a little bit mess and want to make it clean and clear. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173731-5 MX6Q/ARCH :rename gpmi-nfc to gpmi-nandHuang Shijie
rename the gpmi-nfc to gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173731-4 MX6Q/ARCH : add mxs_reset_block()Huang Shijie
add mxs_reset_block() for mx6q. In order to keep the same code as the community, I reduce the parameters to one. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-02-07ENGR00173615 [mx5 mmc]fix mx5 build errorTony Lin
fix build error on mx5 platforms Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-07ENGR00173615-1 [mx6q]add mx6q_revision to common header fileTony Lin
the common API is needed by drivers to distinguish TO version Signed-off-by: Tony Lin <tony.lin@freescale.com>
2012-02-03ENGR00173586-1 [MX6] Add support to source GPT from 24MHzRanjani Vaidyanathan
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced from a constant source (better for frequency scaling). Currently we set the GPT clock to 3MHz (24MHz div by 8). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-02ENGR00173659 MX6Q_UART Change Physical / Virtural Port mappingEric Sun
For ARM2 and Sabreauto, change TTY0 to TTY3 (which is physical UART4) For SabreSD, Change TTY3 to TTY0 (which is physical UART1) Mapping Changed as the following Physical Virtual -------- -------- 1 0 2 1 3 2 4 3 Signed-off-by: Eric Sun <jian.sun@freescale.com>
2012-02-01ENGR00172395-1 MX6Q_ARM2: add sgtl5000 audio driverGary Zhang
add sgtl5000 platform data. VPC board is used to extend sgtl5000 hardware. Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-01-31ENGR00173406-1 MX6Q : fix compiling errorHuang Shijie
add the DMA header to fix the compiling error. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-01-31net: remove mm.h inclusion from netdevice.hAlexey Dobriyan
Remove linux/mm.h inclusion from netdevice.h -- it's unused (I've checked manually). To prevent mm.h inclusion via other channels also extract "enum dma_data_direction" definition into separate header. This tiny piece is what gluing netdevice.h with mm.h via "netdevice.h => dmaengine.h => dma-mapping.h => scatterlist.h => mm.h". Removal of mm.h from scatterlist.h was tried and was found not feasible on most archs, so the link was cutoff earlier. Hope people are OK with tiny include file. Note, that mm_types.h is still dragged in, but it is a separate story. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-01-30ENGR00172475 [USB]Add wakeup entry for USB device on Kernel3.0Tony LIU
- in Kernel 3.0, all the wakeup entry is removed by default, we need add it manually Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-01-25ENGR00172375 MX6Q Sabresd: Enable camera sensorsNancy Chen
1. Enable parallel csi camera sensor, default sensor is ov5640 2. Enable mipi csi2 camera sensor, default sensor is ov5640 3. Rename to sabresd Signed-off-by: Even Xu <b21019@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-01-24ENGR00172676 MX6Q: Add suport for i.MX 6Q Sabre Smart DeviceNancy Chen
Add suport for i.MX 6Quad SABRE Smart Device. Rename to SABRESD. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-01-19ENGR00172374-5: GPIO: use chained_irq_enter/exit pairJason Liu
Kernel oops when plug in/out sd card and throw out null pointer this is due to: commit: 1a01753 ARM: gic: use handle_fasteoi_irq for SPIs commit 1a01753ed90a4fb84357b9b592e50564c07737f7 Author: Will Deacon <will.deacon@arm.com> Date: Wed Feb 9 12:01:12 2011 +0000 ARM: gic: use handle_fasteoi_irq for SPIs Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling. On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux. This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip. Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary. Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs). Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> the above commit has removed the irq_ack from gic chip tus the following call: desc->irq_data.chip->irq_ack(&desc->irq_data); will trow the kernel oops, to fix it, just involve the pair to fix it. chained_irq_enter(chip, desc); chained_irq_exit(chip, desc); This also aligns the upstream kernel doing such as v3.2 Signed-off-by: Jason Liu <r64343@freescale.com>
2012-01-19ENGR00172374-4: remove platform _adjust_dma_zone functionJason Liu
fix the compiling warnings when upgrade to v3.0 arch/arm/mm/init.c:215: warning: 'arm_adjust_dma_zone' defined but not used The commit: be20902 ARM: use ARM_DMA_ZONE_SIZE to adjust the zone sizes by Russell has make the _adjust_dma_zone function the common help function, thus we can remove platform _adjust_dma_zone function by just define:ARM_DMA_ZONE_SIZE commit be20902ba67de70b38c995903321f4152dee57b7 Author: Russell King <rmk+kernel@arm.linux.org.uk> Date: Wed May 11 15:39:00 2011 +0100 ARM: use ARM_DMA_ZONE_SIZE to adjust the zone sizes Rather than each platform providing its own function to adjust the zone sizes, use the new ARM_DMA_ZONE_SIZE definition to perform this adjustment. This ensures that the actual DMA zone size and the ISA_DMA_THRESHOLD/MAX_DMA_ADDRESS definitions are consistent with each other, and moves this complexity out of the platform code. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Jason Liu <r64343@freescale.com>
2012-01-19ENGR00172374-1 i.mx: CPUFREQ: not use cpufreq_debug_printkJason Liu
fix the building errors when upgrade to v3.0 commit: d06d8c [CPUFREQ] use dynamic debug instead of custom infrastructure has removed cpufreq_debug_printk, we will give one update for i.mx driver Signed-off-by: Jason Liu <r64343@freescale.com>
2012-01-19ENGR00169906-3 MXS-DMA : add new flagsHuang Shijie
We catch a DMA timeout bug in the NAND in mx6q. If we do not set the WAIT4END in the middle DMA command structure of the long DMA command chain, a DMA timeout may occurs. In order to fix the bug, we should let the driver to set the proper DMA flags in the DMA command structrues. So add the new flags for MXS-DMA. The driver can use these flags to control the DMA in a flexible way. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-01-19ENGR00171462-1 vpu: add BIT_PIC_RUN register in mxc_vpu.hSammy He
Add BIT_PIC_RUN register definition in mxc_vpu.h of arch/arm Signed-off-by: Sammy He <r62914@freescale.com>
2012-01-19ENGR00171564-2 MX6Q ARM2: Enable TVIN based on AutoBoardEven Xu
- Add TVin platform data - Configure TVin io: such as RESET, POWERDOWN Signed-off-by: Even Xu <b21019@freescale.com>
2012-01-19ENGR00170444: [v3]imx6sabreauto adv7180 TVin portb37753
imx6sabreauto adv7180 TVin port ioexpanders addresss were incorrect, modification in board-mx6q_sabreauto.c was done. adv7180 boot structures and i2c structures were added in board-mx6q_sabreauto.c i2c3 was not configured properly modified in iomux-mx6q.h. Signed-off-by: B37753 <B37753@freescale.com>
2012-01-09ENGR00170938-1 mxc hdmi: Enable HDMI output color space convertSandor Yu
Fix HDMI AVI info frame config register bit define error. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-01-09ENGR00170945:mx6: clk: __clk_disable operates only when usecount > 0wu guoxing
in __clk_disable, check usecount, if it is 0, return, otherwise, the usecount will be un-correct. Signed-off-by: Wu Guoxing <b39297@freescale.com>
2012-01-09ENGR00139278-1: Add MLB driver board level code for mx6qTerry Lv
Add board level code for mlb, including platform data, clock, etc. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-01-09ENGR00170891 [MX6]Disable WAIT mode and DVFSAnson Huang
WAIT mode and DVFS still have some defects, we need to disable it by default until we make them works. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-01-09ENGR00169681 MX6: Add GPIO keys for sabrreliteLin Fuzhen
Add gpio keys for sabrelite Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
2012-01-09ENGR00170518 imx6q-ard: add iomux esai pad settingsAdrian Alonso
* imx6q-sabreauto esai pad settings * Add mux pad setting for esai Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-01-09ENGR00169872-1 rework hdmi initialization and hotplug sequenceAlan Tull
This commit intends to implement the flowchart and details documented in the HDMI Transmitter Controller User Guide section entitled "Programming Model". Some input is also from the Synopsys API code. The HDMI specification requires HDMI to set itself to VGA DVI mode before reading the EDID. So follow this sequence when HDMI is hotplugged: 1. Hdmi connector is plugged in, HDMI video gets an interrupt. 2. Clear out video mode list. Add only VGA DVI mode to list. 3. Request VGA DVI mode (call fb_set_var()) 4. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and call mxc_hdmi_setup() to set up HDMI. 5. Read the edid and add video modes from edid. Select the video mode that is similar to the command line default. 6. Request VGA DVI mode (call fb_set_var()) 7. HDMI video driver will get FB_EVENT_MODE_CHANGE callback and do mxc_hdmi_setup(). Also included is a workaround for an overflow condition in the HDMI. The frame composer has an arithmetic unit that gets updated every time we write to one of the FC registers. But sometimes, depending on the relation between the tmds and sfr clocks, it may happen that this unit doesn't get updated, even though the registers are holding correct values. The workaround for this is, after completing the controller configuration, to rewrite one of the FC registers (i.e. FC_INVIDCONF) three or four times with the same value, and then follow it up by a SW reset to the TMDS clock domain (MC_SWRSTZ). We clear the overflow condition as described above every time we change video mode. Also an overflow interupt handler will clear the overflow condition if it happens again. This overflow condition is expected (and not a problem) when we are in DVI (non-HDMI) mode, so we do not worry about it in that case. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2012-01-09ENGR00169975: imx6sabreauto fix i2c iomux pad settingsAdrian Alonso
* imx6sareauto fix i2c iomux pad settings * On sabreaauto the i2c pad settings are missing in iomux-mx6q.h * update i2c pad seetings and SD2 control pads * Set correct i2c address for io expanders (expander A and B) * explicit assert io expander reset line for normal operation mode Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-01-09ENGR00170434: MX6 - Add support to read Silicon versionRanjani Vaidyanathan
Read the silicon version stored in ROM at address ox48. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-01-09ENGR00170342 PWM: fix pwm output can't be set to 100% full dutyYuxi Sun
The chip document says the counter counts up to period_cycles + 1 and then is reset to 0, so the actual period of the PWM wave is period_cycles + 2 Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-01-09ENGR00170244-1 ARM: AHCI: Enable PDDQ mode when no disk is attachedRichard Zhu
In order to save the power consumption, enable the PDDQ mode of AHCI PHY when there is no sata disk on the port Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-01-09ENGR00170141: Fix debug messages generated by CPUFREQRanjani Vaidyanathan
When dvfs-core is enabled along with "debug" in command line, CPUFREQ printed too many debug messages. Fix this by changing the threshold settings for DVFS-CORE and make the transitions more conservative and infrequent. Also use the CPUFREQ debug flag. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-01-09ENGR00170145-1 ipuv3: add resource for overlay fb buffer reservationXinyu Chen
We have already had framebuffer reservation for BG display by set the base/size resource in fb platform data. But we may also have FG fb buffer reserve requirement. So add addtional base/size resource in fb plaform data, add a IORESROUCE_MEM resource when fb device register to meet such requirement. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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