summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
AgeCommit message (Collapse)Author
2021-04-06Merge tag 'v5.4.109' into 5.4-2.3.x-imxAndrey Zhizhikin
This is the 5.4.109 stable release Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-03-30arm64: dts: ls1046a: mark crypto engine dma coherentHoria Geantă
commit 9c3a16f88385e671b63a0de7b82b85e604a80f42 upstream. Crypto engine (CAAM) on LS1046A platform is configured HW-coherent, mark accordingly the DT node. As reported by Greg and Sascha, and explained by Robin, lack of "dma-coherent" property for an IP that is configured HW-coherent can lead to problems, e.g. on v5.11: > kernel BUG at drivers/crypto/caam/jr.c:247! > Internal error: Oops - BUG: 0 [#1] PREEMPT SMP > Modules linked in: > CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.11.0-20210225-3-00039-g434215968816-dirty #12 > Hardware name: TQ TQMLS1046A SoM on Arkona AT1130 (C300) board (DT) > pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--) > pc : caam_jr_dequeue+0x98/0x57c > lr : caam_jr_dequeue+0x98/0x57c > sp : ffff800010003d50 > x29: ffff800010003d50 x28: ffff8000118d4000 > x27: ffff8000118d4328 x26: 00000000000001f0 > x25: ffff0008022be480 x24: ffff0008022c6410 > x23: 00000000000001f1 x22: ffff8000118d4329 > x21: 0000000000004d80 x20: 00000000000001f1 > x19: 0000000000000001 x18: 0000000000000020 > x17: 0000000000000000 x16: 0000000000000015 > x15: ffff800011690230 x14: 2e2e2e2e2e2e2e2e > x13: 2e2e2e2e2e2e2020 x12: 3030303030303030 > x11: ffff800011700a38 x10: 00000000fffff000 > x9 : ffff8000100ada30 x8 : ffff8000116a8a38 > x7 : 0000000000000001 x6 : 0000000000000000 > x5 : 0000000000000000 x4 : 0000000000000000 > x3 : 00000000ffffffff x2 : 0000000000000000 > x1 : 0000000000000000 x0 : 0000000000001800 > Call trace: > caam_jr_dequeue+0x98/0x57c > tasklet_action_common.constprop.0+0x164/0x18c > tasklet_action+0x44/0x54 > __do_softirq+0x160/0x454 > __irq_exit_rcu+0x164/0x16c > irq_exit+0x1c/0x30 > __handle_domain_irq+0xc0/0x13c > gic_handle_irq+0x5c/0xf0 > el1_irq+0xb4/0x180 > arch_cpu_idle+0x18/0x30 > default_idle_call+0x3c/0x1c0 > do_idle+0x23c/0x274 > cpu_startup_entry+0x34/0x70 > rest_init+0xdc/0xec > arch_call_rest_init+0x1c/0x28 > start_kernel+0x4ac/0x4e4 > Code: 91392021 912c2000 d377d8c6 97f24d96 (d4210000) Cc: <stable@vger.kernel.org> # v4.10+ Fixes: 8126d88162a5 ("arm64: dts: add QorIQ LS1046A SoC support") Link: https://lore.kernel.org/linux-crypto/fe6faa24-d8f7-d18f-adfa-44fa0caa1598@arm.com Reported-by: Greg Ungerer <gerg@kernel.org> Reported-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Acked-by: Greg Ungerer <gerg@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-10arm64: dts: ls1046a: fix dcfg address rangeZyta Szpak
[ Upstream commit aa880c6f3ee6dbd0d5ab02026a514ff8ea0a3328 ] Dcfg was overlapping with clockgen address space which resulted in failure in memory allocation for dcfg. According regs description dcfg size should not be bigger than 4KB. Signed-off-by: Zyta Szpak <zr@semihalf.com> Fixes: 8126d88162a5 ("arm64: dts: add QorIQ LS1046A SoC support") Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-25arm64: dts: layerscape: apply dma-coherent for dwc3 nodesRan Wang
Since dwc3 cache type has been set to cacheable, apply dma-coherent to all dwc3 nodes accordingly. Note: For LS1043A and LS1046A, since QE-HDLC still doesn't support dma-coherent, we cannot directly revert cd1a4f3c (sdk: dts: ls104x move dma-coherent from soc to its child nodes) to recover dma-coherent for soc. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-12-19LF-387-5 arm64: dts: layerscape: add chip-specific compatible string to usb ↵Ran Wang
nodes To allow USB dwc3 driver to conduct some chip-scpeific configuring. Cover all arm64 based Layerscape SoCs. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Reviewed-by: Leo Li <leo.li@nxp.com>
2019-11-25arm64: dts: ls1012a/ls1043a/ls1046a/ls1088a/ls208xa: replace ftm0 with ↵Biwen Li
ftm_alarm0 The patch replaces ftm0 with ftm_alarm0 DT node - replace ftm0 with ftm_alarm0 - add new rcpm node - remove old rcpm node - aliases ftm_alarm0 as rtc1 Signed-off-by: Biwen Li <biwen.li@nxp.com>
2019-11-25arm64: dts: fsl: remove backplane supportFlorinel Iordache
Remove entire backplane support from device tree for all supported platforms Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
2019-11-25arm64: dts: Fix DWC3 IP VBUS glitch issue on Layerscape platformsRan Wang
Cover LS1012A, LS1043A, LS1046A, LS1088A, LS208xA, LX2160A Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-11-25arm64: dts: ls104x: constrain sata dma address sizeLaurentiu Tudor
Limit the dma mask size for sata to 40 bits to match the actual address size generated towards the interconnect. Re-use the already existing auxiliary simple bus meant for usb but drop the usb reference from the node name. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: nxp: add more thermal zone supportYuantian Tang
To enable all the supported thermal sensors, add sensor id information to thermal zone node. Dts for ls1012a, ls1046a, ls1043a, ls1088a are updated. Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
2019-11-25arm64: dts: ls104x: use a pseudo-bus to constrain usb dma sizeLaurentiu Tudor
Wrap the usb controllers in an intermediate simple-bus and use it to constrain the dma address size of these usb controllers to the 40 bits that they generate toward the interconnect. This is required because the SoC uses 48 bits address sizes and this mismatch would lead to smmu context faults because the usb generates 40-bit addresses while the smmu page tables are populated with 48-bit wide addresses. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: make dma-coherent global to the SoCLaurentiu Tudor
These SoCs are really completely dma coherent in their entirety so add the dma-coherent property at the soc level in the device tree and drop the instances where it's specifically added to a few select devices. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: add iommu-map to pci controllersLaurentiu Tudor
The pci controllers are also behind the smmu so add the iommu-map property to reflect this. The bootloader needs to patch the stream id ranges to some sane values. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: add missing dma ranges propertyLaurentiu Tudor
These chips have a 48-bit address size so make sure that the dma-ranges reflects this. Otherwise the linux kernel's dma sub-system will set the default dma masks to full 64-bit, badly breaking dmas. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104xa: set mask to drop TBU ID from StreamIDLaurentiu Tudor
The StreamID entering the SMMU is actually a concatenation of the SMMU TBU ID and the ICID configured in software. Since the TBU ID is internal to the SoC and since we want that the actual the ICID configured in software to enter the SMMU witout any additional set bits, mask out the TBU ID bits and leave only the relevant ICID bits to enter SMMU. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls1046a: add smmu nodeLaurentiu Tudor
This allows for the SMMU device to be probed by the SMMU kernel driver. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls1046a: accumulated change to ls1046a boardsLi Yang
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce Author: Peng Ma <peng.ma@nxp.com> Date: Wed Jul 25 08:53:07 2018 +0000 dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node support add block-offset to support different virtual block offset for qdma base on soc; the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual block,N based on block number of qdma; Signed-off-by: Peng Ma <peng.ma@nxp.com> commit 46123df3a174f0d76c8b954a0386e64841453836 Author: Florinel Iordache <florinel.iordache@nxp.com> Date: Thu Aug 9 12:29:18 2018 +0300 arm64: dts: updates for Unified Backplane driver Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> commit c08136017e8b18eb58b153129487c5dc760afd20 Author: Florinel Iordache <florinel.iordache@nxp.com> Date: Thu Aug 9 12:23:42 2018 +0300 arm64: dts: ls1046: add support for 10GBase-KR Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> commit 8473f478783f6f601e1c6d7e6afba49a13f3a6a3 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com> Date: Mon Apr 2 16:24:33 2018 +0800 arm64: dts: ls1046a: add dts entry for A-010650 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit 3159fe9263fb145601ccb07fcb9336a68fba4e08 Author: Bao Xiaowei <xiaowei.bao@nxp.com> Date: Fri Oct 13 11:04:39 2017 +0800 arm64: dts: ls1046a: add the property of IB and OB Add the property of inbound and outbound windows number for ep driver. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> commit c8fed58f3c9a0219fda0467791f61abd86eb97f3 Author: Abhimanyu Saini <abhimanyu.saini@nxp.com> Date: Wed Jan 24 22:56:48 2018 +0530 arm64: dts: freescale: ls1046a: Modify DT nodes for qspi Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> commit 96558859ea3a4af44c0b25441f7574ae6222509a Author: Ran Wang <ran.wang_1@nxp.com> Date: Fri Jan 5 15:17:23 2018 +0800 arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Enable USB3 HW LPM feature for ls1046a and active patch for snps erratum A-010131. It will disable U1/U2 temperary when initiate U3 request. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d Author: Zhang Ying-22455 <ying.zhang22455@nxp.com> Date: Tue Jun 13 13:14:26 2017 +0800 arm64: dts: correct the register range of dcfg Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit 67c82e3c7b376139d7cee624589bedbc311f8868 Author: jiaheng.fan <jiaheng.fan@nxp.com> Date: Thu May 11 17:36:33 2017 +0800 arm64: dts: ls1021/ls1043/ls1046: add qdma nodes Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com> commit 4a6cef0c83748ee4f6641489fc324bd64095485d Author: Chenhui Zhao <chenhui.zhao@nxp.com> Date: Fri May 5 17:53:27 2017 +0800 arm64: dts: ls1046a: add ftm0 node Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2019-08-22arm64: dts: fsl: Remove num-lanes property from PCIe nodesHou Zhiqiang
Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-03-22arm64: dts: fsl: Remove unused properties from FSL QSPI nodesFrieder Schrempf
After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-09Merge tag 'pci-v5.1-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - Use match_string() instead of reimplementing it (Andy Shevchenko) - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada) - Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) - Fix DPC use of uninitialized data (Dongdong Liu) - Probe bridge window attributes only once at enumeration-time to fix device accesses during rescan (Bjorn Helgaas) - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du Changbin) - Use config header type (not class code) identify bridges more reliably (Honghui Zhang) - Work around Intel Denverton incorrect Trace Hub BAR size reporting (Alexander Shishkin) - Reorder pciehp cached state/hardware state updates to avoid missed interrupts (Mika Westerberg) - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann) - Mark expected switch fall-through (Mathieu Malaterre) - Use of_node_name_eq() for node name comparisons (Rob Herring) - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang) - Consolidate Rohm Vendor ID definitions (Andy Shevchenko) - Use u32 (not __u32) for things not exposed to userspace (Logan Gunthorpe) - Fix locking semantics of bus and slot reset interfaces (Alex Williamson) - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang) - Allow portdrv to claim subtractive decode Ports so PCIe services will work for them (Honghui Zhang) - Report PCIe links that become degraded at run-time (Alexandru Gagniuc) - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt hotplug (Mika Westerberg) - Revert runtime PM suspend/resume callbacks that broke PME on network cable plug (Mika Westerberg) - Disable Data Link State Changed interrupts to prevent wakeup immediately after suspend (Mika Westerberg) - Extend altera to support Stratix 10 (Ley Foon Tan) - Allow building altera driver on ARM64 (Ley Foon Tan) - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint maintainer (Lorenzo Pieralisi) - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro) - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) - Configure MPS settings for VMD root ports (Jon Derrick) * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits) PCI: Update PCIEPORTBUS Kconfig help text PCI: Fix "try" semantics of bus and slot reset PCI/LINK: Report degraded links via link bandwidth notification dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 PCI: altera: Enable driver on ARM64 PCI: altera: Add Stratix 10 PCIe support PCI/PME: Fix possible use-after-free on remove PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ...
2019-02-21arm64: dts: Add the PCIE EP node in dtsXiaowei Bao
Add the PCIE EP node in dts for ls1046a. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com> Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com> Reviewed-by: Rob Herring <robh+dt@kernel.org>
2019-01-12arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 nodeRan Wang
Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11arm64: dts: fsl: ls1046a: disable uarts by defaultAlexandre Belloni
Disable the UARTs by defaultto avoid registering unused UARTs. This effectively change the number of registered UARTS for the RDB and QDS from 4 to 2 but this seems the right thing to do. It is especially useful when connecting other 8250 uart on PCIe for example as the default maximum number of 8250 UARTs that can be registered is 4. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11arm64: dts: fsl: ls1046a: disable the flash controller by defaultAlexandre Belloni
Set the Integrated Flash Controller status to disabled so each board has the option to enable it. All the existing users have status = "okay" so there is no functional change. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11arm64: dts: layerscape: add num-viewport property for PCIe DT nodesHou Zhiqiang
Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: ls1046a: add qdma device tree nodesPeng Ma
add the qDMA device tree nodes for LS1046A devices. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: layerscape: removed compatible string "snps,dw-pcie"Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add the status property disable PCIeBao Xiaowei
Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-26arm64: dts: fsl: Fix I2C and SPI bus warningsRob Herring
dtc has new checks for I2C and SPI buses. Fix the SPI bus node names and warnings in unit-addresses. arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@57: I2C bus unit address format error, expected "53" arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@56: I2C bus unit address format error, expected "52" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Li Yang <leoyang.li@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03arm64: dts: fsl: remove big-endian field from IFC controllerPrabhakar Kushwaha
As per IFC binding, Absence of "little-endian" field causes registers access in big-endian mode. So no need to set explicit big-endian field IFC node for LS1043A and LS1046A. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-08-25Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "A couple of late-merged changes that would be useful to get in this merge window: - Driver support for reset of audio complex on Meson platforms. The audio driver went in this merge window, and these changes have been in -next for a while (just not in our tree). - Power management fixes for IOMMU on Rockchip platforms, getting closer to kexec working on them, including Chromebooks. - Another pass updating "arm,psci" -> "psci" for some properties that have snuck in since last time it was done" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: iommu/rockchip: Move irq request past pm_runtime_enable iommu/rockchip: Handle errors returned from PM framework arm64: rockchip: Force CONFIG_PM on Rockchip systems ARM: rockchip: Force CONFIG_PM on Rockchip systems arm64: dts: Fix various entry-method properties to reflect documentation reset: imx7: Fix always writing bits as 0 reset: meson: add meson audio arb driver reset: meson: add dt-bindings for meson-axg audio arb
2018-08-24arm64: dts: Fix various entry-method properties to reflect documentationAmit Kucheria
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Fix the cpu-capacity.txt documentation that uses the incorrect value so we don't get copy-paste errors like these. Clarify the language in idle-states.txt by removing the reference to the psci bindings that might be causing this confusion. Finally, fix devicetrees of various boards to reflect current documentation. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-03arm64: dts: freescale: Add missing cooling device properties for CPUsViresh Kumar
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19arm64: dts: freescale: Update to use SPDX identifiersLi Yang
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-01arm64: dts: ls1046a: add a dummy memory 'reg' propertyShawn Guo
The memory node in fsl-ls1046a.dtsi has no 'reg' property, and causes the dtc warning below. Warning (unit_address_vs_reg): Node /memory@80000000 has a unit name, but no reg property Let's add a 'reg' property with dummy memory size, since bootloader will need to fill the correct one per board memory configuration anyway. Cc: Mingkai Hu <Mingkai.Hu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com>
2018-02-24arm64: dts: fsl: update the cpu idle nodeYuantian Tang
According to PSCI standard v0.2, for CPU_SUSPEND call, which is used by cpu idle framework, bit[16] of state parameter must be 0. So update bit[16] of property 'arm,psci-suspend-param', which is used as state parameter, to 0. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12arm64: dts: ls1046a: Move cpu_thermal out of bus nodeFabio Estevam
Move cpu_thermal node from soc node to root node. cpu_thermal node does not have any register properties and thus shouldn't be placed on the bus. This fixes the following build warnings with W=1: arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-11-16Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM device-tree updates from Arnd Bergmann: "We add device tree files for a couple of additional SoCs in various areas: Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking, Amlogic A113D for audio, and Renesas R-Car V3M for automotive. As usual, lots of new boards get added based on those and other SoCs: - Actions S500 based CubieBoard6 single-board computer - Amlogic Meson-AXG A113D based development board - Amlogic S912 based Khadas VIM2 single-board computer - Amlogic S912 based Tronsmart Vega S96 set-top-box - Allwinner H5 based NanoPi NEO Plus2 single-board computer - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers - Allwinner A83T based TBS A711 Tablet - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8 - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500 wireless access points and routers - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board - NXP i.MX53 based GE Healthcare PPD biometric monitor - NXP i.MX6 based Pistachio single-board computer - NXP i.MX6 based Vining-2000 automotive diagnostic interface - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards - Renasas r8a7745 based iWave G22D-SODIMM SoM - Rockchip rk3288 based Amarula Vyasa single-board computer - Samsung Exynos5800 based Odroid HC1 single-board computer For existing SoC support, there was a lot of ongoing work, as usual most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic and Allwinner platforms, but others were also active. Rob Herring and many others worked on reducing the number of issues that the latest version of 'dtc' now warns about. Unfortunately there is still a lot left to do. A rework of the ARM foundation model introduced several new files for common variations of the model" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits) arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3 dt-bindings: bus: Add documentation for the Technologic Systems NBUS arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock ARM: dts: owl-s500: Add CubieBoard6 dt-bindings: arm: actions: Add CubieBoard6 ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock ARM: dts: owl-s500: Set power domains for CPU2 and CPU3 arm: dts: mt7623: remove unused compatible string for pio node arm: dts: mt7623: update usb related nodes arm: dts: mt7623: update crypto node ARM: dts: sun8i: a711: Enable USB OTG ARM: dts: sun8i: a711: Add regulator support ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1 ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1 ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes ARM: dts: sunxi: Add dtsi for AXP81x PMIC arm64: dts: allwinner: H5: Restore EMAC changes ...
2017-10-13arm64: dts: update the DPAA QBMan nodesMadalin Bucur
Use constants in the interrupt description. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-10-12arm64: dts: ls1046a: Add PCIe controller DT nodesHou Zhiqiang
LS1046a implements 3 PCIe 3.0 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2017-09-22arm64: dts: ls: Add optee nodeSumit Garg
Add optee device tree node on ls1012a, ls1043a, ls1046a, ls1088a and ls208xa. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-08-31arm64: dts: ls1046a: Add MSI dts nodeMinghuan Lian
LS1046a includes 3 MSI controllers. Each controller supports 128 interrupts. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-06-05arm64: dts: ls1046a: Add dis_rxdet_inp3_quirk property to USB3 nodeRan Wang
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-21arm64: dts: add LS1046A DPAA FMan nodesMadalin Bucur
Add the DPAA 1.x FMan device tree nodes for LS1046A boards. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-16arm64: dts: add LS1046A DPAA QBMan nodesMadalin Bucur
Add the QBMan device tree nodes for LS1046A devices. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: ls1046a: support SD UHS-I and eMMC HS200 on RDBYangbo Lu
This patch is to enable SD UHS-I mode and eMMC HS200 mode on LS1046ARDB in dts. Also, the eSDHC peripheral clock must be used instead of platform clock to support these modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: Define big endian of IFC for LS1043a/LS1046aPrabhakar Kushwaha
Integrated flash controller present in LS1043A and LS1046A is big endian. So add big endian property in the devive tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: freescale: update the copyright claimsLi Yang
Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-08arm64: dts: added ecc register address to sata node on ls1046aTang Yuantian
For ls1046 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-26 00:33:41 +0000