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2022-05-02arch: arm64: dts: lx2160a: describe the SerDes block #1Ioana Ciornei
Describe the SerDes block #1 using the generic phys infrastructure. This way, the ethernet nodes can each reference their serdes lanes individually using the 'phys' dts property. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from commit 3cbe93a1f540dbc997fc24a38796266e2b473e06) Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2021-11-24arm64: dts: lx2160a: add chip information and dma-coherent in dwc3 nodesRan Wang
To allow USB dwc3 driver to conduct some chip-scpeific snooping configuring. [ Leo: binding not upstreamed ] Since dwc3 cache type has been set to cacheable, apply dma-coherent to all dwc3 nodes accordingly. [ Leo: kernel driver changes dropped in upstream, however u-boot are setting cache types now. Going forward should rely on u-boot to set the dma-coherent. ] Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com>
2021-11-24arm64: dts: lx2160a: Fix DWC3 IP VBUS glitch issueRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [ Leo: driver change and binding not upstreamed ]
2021-11-24arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodesRan Wang
Enable USB3 HW LPM feature for lx2160a. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2021-11-24arm64: dts: lx2160a: add pcie EP mode nodesXiaowei Bao
The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2021-11-24arm64: dts: lx2160a: update PCIe nodes to match rev2 siliconLi Yang
The original dts was created based on the non-production rev1 silicon which was only used for evaluation. Update the PCIe nodes to align with the different controller used in production rev2 silicon. Signed-off-by: Li Yang <leoyang.li@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2021-11-24arm64: dts: lx2160a: add optee-tz nodePankaj Gupta
Disabled by default in SoC dtsi and enables in board dts files. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2021-11-09arm64: dts: lx2160a: fix scl-gpios property nameZhang Ying-22455
Fix the typo in the property name. Signed-off-by: Zhang Ying <ying.zhang22455@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2021-06-12arm64: dts: freescale: Separate each group of data in the property 'reg'Zhen Lei
Do not write the 'reg' of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: soc: pcie@3400000:reg:0: \ [0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30arm64: dts: lx2160a: Add flexcan supportKuldeep Singh
LX2160A supports two flexcan controllers. Add the support. Enable support further for LX2160A-RDB/QDS. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-11arm64: dts: lx2160a: use constants in the clockgen phandleMichael Walle
Now that we have constants, use them. This is just a mechanical change. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05arm64: dts: lx2160a: add DT node for external interrupt linesBiwen Li
Add device-tree node for external interrupt lines IRQ0-IRQ11. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: lx2160a: add PCS MDIO and PCS PHY nodesIoana Ciornei
Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along with their internal PCS PHYs, which will be used when the DPMAC is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22arm64: dts: layerscape: Add label to pcie nodesWasim Khan
Add label to pcie nodes so that they are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13arm64: dts: lx2160a: Increase configuration space sizeWasim Khan
lx2160a rev2 requires 4KB space for type0 and 4KB space for type1 iATU window. Increase configuration space size to 8KB to have sufficient space for type0 and type1 window. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Li Yang <leoyang.li@nxp.com> Acked-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-11arm64: dts: lx2160a: add ftm_alarm0 DT nodeBiwen Li
The patch adds ftm_alarm0 DT node for Soc LX2160A FlexTimer1 module is used to wakeup the system in deep sleep Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-11arm64: dts: lx2160a: add dspi controller DT nodesChuanhua Han
Add the dspi support on lx2160 Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29arm64: dts: lx2160a: add more thermal zone supportYuantian Tang
There are 7 thermal zones in lx2160a soc. Add the rest thermal zone node to enable them. Also correct one of the values for tmu-calibration property. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11arm64: dts: layerscape: add iommu-map property to pci nodesHou Zhiqiang
Add the iommu-map property to the pci nodes so that the firmware fixes it up with the required values thus enabling iommu for devices connected over pci. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24arm64: dts: lx2160a: Add PCIe controller DT nodesHou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23arm64: dts: lx2160a: add emdio2 nodeRussell King
Add a description for the emdio2 controller to the lx2160a dtsi file, so we can use it in the SolidRun Clearfog CX platform. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11arm64: dts: lx2160a: add emdio1 nodeIoana Ciornei
Add the External MDIO1 device node found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-06Merge tag 'imx-dt64-tmu-5.5' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt LX2160A TMU support for 5.5: - Add TMU (Thermal Monitoring Unit) device node to enable thermal support on LX2160A SoC. * tag 'imx-dt64-tmu-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: lx2160a: add tmu device node ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk ARM: dts: imx7s: Correct GPT's ipg clock source ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect' ARM: dts: imx6q-logicpd: Re-Enable SNVS power key arm64: dts: lx2160a: Correct CPU core idle state name arm64: dts: zii-ultra: fix ARM regulator states soc: imx: imx-scu: Getting UID from SCU should have response Link: https://lore.kernel.org/r/20191105150315.15477-6-shawnguo@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-28arm64: dts: lx2160a: add tmu device nodeYuantian Tang
Add the TMU (Thermal Monitoring Unit) device node to enable TMU feature. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-14arm64: dts: lx2160a: Correct CPU core idle state nameRan Wang
lx2160a support PW15 but not PW20, correct name to avoid confusing. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Fixes: 00c5ce8ac023 ("arm64: dts: lx2160a: add cpu idle support") Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-07arm64: dts: mark lx2160a esdhc controllers dma coherentRussell King
The LX2160A esdhc controllers are setup by the driver to be DMA coherent, but without marking them as such in DT, Linux thinks they are not. This can lead to random sporadic DMA errors, even to the extent of preventing boot, such as: mmc0: ADMA error mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202 mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013 mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038 mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8 mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001 mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202 mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00 mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33 mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00 mmc0: sdhci: Host ctl2: 0x00000000 mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c mmc0: sdhci: ============================================ mmc0: error -5 whilst initialising SD card These are caused by the device's descriptor fetch hitting speculatively loaded CPU cache lines that the CPU does not see through the normal, non-cacheable DMA coherent mapping that it uses for non-coherent devices. DT and the device must agree wrt whether the device is DMA coherent or not. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19arm64: dts: lx2160a: Fix incorrect I2C clock dividerChuanhua Han
Lx2160a platform, the i2c input clock is actually platform pll CLK / 16 (this is the hardware connection), other clock divider can not get the correct i2c clock, resulting in the output of SCL pin clock is not accurate. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03arm64: dts: add the console node for DPAA2 platformsIoana Ciornei
Add the console device tree node for the following DPAA2 based platforms: LS1088A, LS2080A, LS2088A and LX2160A. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-15arm64: dts: fsl: add ptp timer node for dpaa2 platformsYangbo Lu
This patch is to add ptp timer device tree node for dpaa2 platforms(ls1088a/ls208xa/lx2160a). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-22arm64: dts: lx2160a: add cpu idle supportRan Wang
lx2160a supports pw20 which could help save more power during cpu is dile. It needs system firmware support via PSCI. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11arm64: dts: lx2160a: add sata node supportPeng Ma
Add SATA device nodes for fsl-lx2160a and enable support for QDS and RDB boards. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01arm64: dts: lx2160a: add FlexSPI node propertyYogesh Narayan Gaur
Add fspi node property for LX2160A SoC for FlexSPI driver. Property added for the FlexSPI controller and for the connected slave device for the LX2160ARDB target. This is having two SPI-NOR flash device, mt35xu512aba, connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: lx2160a: Add dma-ranges propertyIoana Ciocoi Radulescu
Add missing property from the soc node in LX2160A dts. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: lx2160a: Add fsl-mc nodeIoana Ciocoi Radulescu
Add the fsl-mc node in the LX2160A device tree. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 nodeRan Wang
Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-05arm64: dts: add QorIQ LX2160A SoC supportVabhav Sharma
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-02 21:37:53 +0000