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path: root/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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2020-02-26arm64: dts: lx2160a: add iommu-map property to pci nodesLaurentiu Tudor
Add the iommu-map property to the pci nodes so that the firmware fixes it up with the required values thus enabling iommu for devices connected over pci. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> (cherry picked from commit 94db63e57e5150e693ab39a3195a0ac02000fb05)
2019-12-25arm64: dts: layerscape: apply dma-coherent for dwc3 nodesRan Wang
Since dwc3 cache type has been set to cacheable, apply dma-coherent to all dwc3 nodes accordingly. Note: For LS1043A and LS1046A, since QE-HDLC still doesn't support dma-coherent, we cannot directly revert cd1a4f3c (sdk: dts: ls104x move dma-coherent from soc to its child nodes) to recover dma-coherent for soc. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-12-19LF-387-5 arm64: dts: layerscape: add chip-specific compatible string to usb ↵Ran Wang
nodes To allow USB dwc3 driver to conduct some chip-scpeific configuring. Cover all arm64 based Layerscape SoCs. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Reviewed-by: Leo Li <leo.li@nxp.com>
2019-11-27arm64: dts: lx2160a: add tmu device nodeYuantian Tang
Add the TMU (Thermal Monitoring Unit) device node to enable TMU feature. Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
2019-11-25arm64: dts: lx2160a: add ftm_alarm0 DT nodeBiwen Li
The patch adds ftm_alarm0 DT node for Soc LX2160A FlexTimer1 module is used to wakeup the system in deep sleep Signed-off-by: Biwen Li <biwen.li@nxp.com>
2019-11-25arm64: dts: fsl: remove backplane supportFlorinel Iordache
Remove entire backplane support from device tree for all supported platforms Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
2019-11-25arm64: dts: fsl: lx2160a: add flexcan nodePankaj Bansal
Add flexcan node in LX2160A SOC file as well as in QDS and RDB files. The device tree bindings used can be referred from Documentation/devicetree/bindings/net/can/fsl-flexcan.txt Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
2019-11-25arm64: dts: lx2160a: Enable usb3-lpm-capable for usb3 nodeRan Wang
Enable USB3 HW LPM feature for lx2160a and active patch for snps erratum A-010131. It will disable U1/U2 temperary when initiate U3 request. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-11-25arm64: dts: fsl: layerscape: fix warnings when compiling dts filesPankaj Bansal
when compiling dts file using DTC_FLAG='-@', the device tree compiler reports these warnings: Warning (simple_bus_reg): /soc/mdio@0x8c0b000: simple-bus unit address format error, expected "8c0b000" Warning (unit_address_format): /pfe@04000000: unit name should not have leading 0s Fixed the node names to silence these warnings. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
2019-11-25arm64: dts: freescale: lx2160a: add pcie EP mode DT nodesXiaowei Bao
The LX2160A PCIe EP mode node. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
2019-11-25arm64: dts: Fix DWC3 IP VBUS glitch issue on Layerscape platformsRan Wang
Cover LS1012A, LS1043A, LS1046A, LS1088A, LS208xA, LX2160A Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-11-25arm64: dts: lx2160aqds: Add mdio mux nodesPankaj Bansal
The two external MDIO buses used to communicate with phy devices that are external to SOC are muxed in LX2160AQDS board. These buses can be routed to any one of the eight IO slots on LX2160AQDS board depending on value in fpga register 0x54. Additionally the external MDIO1 is used to communicate to the onboard RGMII phy devices. The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga register. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
2019-11-25arm64: dts: lx2160a: add optee-tz nodePankaj Gupta
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2019-11-25arm64: dts: freescale: lx2160a: add pcie DT nodesHou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25arm64: dts: Added endianness information to dts serdes nodeFlorinel Iordache
This change is required to specify that serdes HW peripheral is little-endian. Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
2019-11-25arm64: dts: lx2160: Add all pcs mdio definitions according to RMFlorinel Iordache
This change is required in preparation for adding 40GBase-KR support in DTS for LX2160 Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
2019-11-25arm64: dts: lx2160a: add dspi controller DT nodesChuanhua Han
Add the dspi support on lx2160 Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25arm64: dts: lx2160a: correct scl-gpios propertyZhang Ying-22455
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2019-11-25arm64: dts: lx2160a: add MDIO device-tree nodesVicentiu Galanopulo
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
2019-10-14arm64: dts: lx2160a: Correct CPU core idle state nameRan Wang
lx2160a support PW15 but not PW20, correct name to avoid confusing. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Fixes: 00c5ce8ac023 ("arm64: dts: lx2160a: add cpu idle support") Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19arm64: dts: lx2160a: Fix incorrect I2C clock dividerChuanhua Han
Lx2160a platform, the i2c input clock is actually platform pll CLK / 16 (this is the hardware connection), other clock divider can not get the correct i2c clock, resulting in the output of SCL pin clock is not accurate. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03arm64: dts: add the console node for DPAA2 platformsIoana Ciornei
Add the console device tree node for the following DPAA2 based platforms: LS1088A, LS2080A, LS2088A and LX2160A. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-15arm64: dts: fsl: add ptp timer node for dpaa2 platformsYangbo Lu
This patch is to add ptp timer device tree node for dpaa2 platforms(ls1088a/ls208xa/lx2160a). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-22arm64: dts: lx2160a: add cpu idle supportRan Wang
lx2160a supports pw20 which could help save more power during cpu is dile. It needs system firmware support via PSCI. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11arm64: dts: lx2160a: add sata node supportPeng Ma
Add SATA device nodes for fsl-lx2160a and enable support for QDS and RDB boards. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01arm64: dts: lx2160a: add FlexSPI node propertyYogesh Narayan Gaur
Add fspi node property for LX2160A SoC for FlexSPI driver. Property added for the FlexSPI controller and for the connected slave device for the LX2160ARDB target. This is having two SPI-NOR flash device, mt35xu512aba, connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: lx2160a: Add dma-ranges propertyIoana Ciocoi Radulescu
Add missing property from the soc node in LX2160A dts. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: lx2160a: Add fsl-mc nodeIoana Ciocoi Radulescu
Add the fsl-mc node in the LX2160A device tree. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 nodeRan Wang
Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-05arm64: dts: add QorIQ LX2160A SoC supportVabhav Sharma
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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