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The power domain for clocks is not needed by audio drivers, which
is handled by clock driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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Enable SAI/ASRC/WM8960
1. Update the interrupt number for audio modules
2. Enable 3 wm8960 codecs
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Split dma channel power domain from sub-domain of dma customer driver
such as Audio, LPUART etc.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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The mem clock is used to access the register, if there is no
mem clock defined, we should use the ipg clock instead,
otherwise there will be kernel dump after system reboot.
[ 3.010962] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 3.010964] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.19.35-05057-g2134d856e6b2 #2889
[ 3.010966] Hardware name: Freescale i.MX8QXP MEK (DT)
[ 3.010968] Call trace:
[ 3.010969] dump_backtrace+0x0/0x178
[ 3.010971] show_stack+0x14/0x20
[ 3.010972] dump_stack+0x8c/0xac
[ 3.010974] panic+0x120/0x28c
[ 3.010975] __stack_chk_fail+0x0/0x18
[ 3.010977] arm64_serror_panic+0x74/0x80
[ 3.010979] do_serror+0x68/0x130
[ 3.010980] el1_error+0x7c/0xdc
[ 3.010982] _raw_spin_unlock_irqrestore+0xc/0x48
[ 3.010984] clk_core_disable_lock+0x28/0x38
[ 3.010985] clk_disable+0x1c/0x30
[ 3.010987] regmap_mmio_write+0x54/0x68
[ 3.010989] _regmap_bus_reg_write+0x14/0x20
[ 3.010990] _regmap_write+0x60/0xa8
[ 3.010992] regmap_write+0x48/0x70
[ 3.010994] fsl_asrc_probe+0x258/0x660
[ 3.010995] platform_drv_probe+0x50/0xb0
Why this issue only happen at kernel reboot, it is because the ipg
clock is enabled in default after system reset, after used once, the
ipg clock is disabled, then reboot system, the issue happen.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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enable ARC for HDMI Audio
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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update compatible string for esai
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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enable audio sound card (dsp, amix, asrc, esai, sai, cs42888, wm8960)
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Due to SCU SAI4&5 clock is still not registered.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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