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Commit ee96e9f815d6 ("MLK-24368-1 arm64: dts: imx8qm: Add support for USBH1")
caused i.MX8DXL USB PHYs to not go into low power mode via runtime suspend.
Fix it by moving the usbh1, usbmisc2 and usbphynop2 to the specific
imx8qm-ss-conn.dtsi file.
While at it, change the usbphynop2 status as disabled.
Reviewed-by: Jun Li <jun.li@nxp.com>
Tested-by: Sebastien Haezebrouck <sebastien.haezebrouck@nxp.com>
Reported-by: Sebastien Haezebrouck <sebastien.haezebrouck@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add support for USBH1 on imx8qm, USBH1 is a HSIC controller
Reviewed-by: Jun Li <jun.li@nxp.com>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Alifer Moraes <alifer.moraes@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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SLSLICE[2] cannot be accessed on 8DXL platform since it is
fixed and locked clock, but can be accessed on 8qm/8qxp platforms
who want to assign the clock to 250Mhz.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Enable legacy enet0 port to support daughter RGMII AR8031
PHY board.
imx8dxl evk board rework:
- Remove U30, R181, R182
- Connect U30.2 -U30.7
- Connect U30.3 ->U30.6
- Change R178/R179 to 1.5K
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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IC confirmed the both imx8qm and imx8qxp could use 250M as usb3_clk
and no performance drop.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add mlb dts file for imx8qxp-lpddr4-val platform.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
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add gpmi-nand dts for nand support on imx8qxp val
Signed-off-by: Han Xu <han.xu@nxp.com>
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On imx8qxp and imx8qm mek board, usdhc1 is for eMMC usage, and will work at
HS400 mode, this HS400 mode will work at 200MHz, and will default divide 2 from
source clock(IMX_SC_R_SDHC_0), which mean we need to config the source clock
to 400MHz at least.
Before this patch, HS400 mode only work at 100MHz, and will meet some timeout issue
when do system suspend/resume, due to our HS400 related timing setting is based on
the 200MHz. Also, HS400 work at 100MHz will impact the performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
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Add Cadence USB3 support
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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switch to new lpcg clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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switch to two cell scu clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Add conn lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.
Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.
NOTE: this is a complementary patch of
c24fc267a8a9 ("arm64: dts: imx8qxp: orginize dts in subsystems"
based on latest upstream versions.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Enable enet2 port for MEK board.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
[ Aisheng: fix small conflicts during upgrade ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Currently enet cannot work due to the wrong clock tree and
incorrect IO voltage, correct them.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add NXP USB2 controller and PHY node
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add SD3.0 support, and make usdhc support eMMC V5.1
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.
Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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