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2012-04-28ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400MWayne Zou
On mx6dl, set ipu2_clk's parent from pll2_pfd_400M. On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-28ENGR00181107 add dma_alloc_writethrough functionSandor Yu
add dma_alloc_writethrough function to dma_mapping.c Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-04-27ENGR00180424: Changed iomux ID pinGuillermo
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID Signed-off-by: Guillermo <b12356@freescale.com>
2012-04-27ENGR00180076: prompt "mmc0: error -110 during resume" with atheros wifi cardjustin.jiang
* only happend on sabre-auto board,atheros sdio wifi card can't be used after suspend/resume * Fix by keeping sdio power at suspend. Signed-off-by: justin.jiang <b31011@freescale.com>
2012-04-26ENGR00180882- MX6DL Add bus frequency scaling support.Ranjani Vaidyanathan
Added support for changing DDR frequency on MX6DL. During system IDLE, DDR freq can drop down to 24MHz if none of the devices that need high AHB frequency are active. Changed the DDR code to handle both MX6Q and MX6DL DDR and IOMUX settings. Fixed bug associated incorrect IRAM memory allocation used to store DDR and IOMUX data. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-26ENGR00180185: MX6-Add support for low power audio playbackRanjani Vaidyanathan
The DDR frequency needs to be at 50MHz for low power audio playback. So added a new low power mode for audio. Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-20ENGR00180412 MX6 SATA: Enable PHY in the SATA initilizationRichard Zhu
iENGR00179574: MX6- Add bus frequency scaling support disable SATA PHY defaultly Enable PHY in the SATA initilization, make sure the SATA work well. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-19ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1Richard Zhu
* Adjust the parameters, enlarge the eye diagram. * Force to the PCIE GEN1 speed. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-19ENGR00180096 change NAND clock source to pll2_pfd_400MAllen Xu
change clock source explicitly by calling set_parent() function Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400MAllen Xu
Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to pll2_pfd_400M. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-17ENGR00179685 MX6 clock:Cleanup LDB DI parent clockLiu Ying
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1. However, MX6DL uses mmdc_ch1 as LDB DI parent clock. This patch corrects the LDB DI parent clock setting. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-16ENGR00179747: MX6DL-Fix boot failureRanjani Vaidyanathan
Fix the boot failure caused by: 8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab MX6- Add bus frequency scaling support There is no SATA on MX6DL. Accessing SATA PHYs early in the boot process causes the system to crash. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-16ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1Liu Ying
This patch corrects LDB DI clock's parent clock to be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0 according to ticket TKT071080(0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1). Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-04-13ENGR00179574: MX6- Add bus frequency scaling supportRanjani Vaidyanathan
Add support for scaling the bus frequency (both DDR and ahb_clk). The DDR and AHB_CLK are dropped to 24MHz when all devices that need high AHB frequency are disabled and the CORE frequency is at the lowest setpoint. The DDR is dropped to 400MHz for the video playback usecase. In this mode the GPU, FEC, SATA etc are disabled. To scale the bus frequency, its necessary that all cores except the core that is executing the DDR frequency change are in WFE. This is achieved by generating interrupts on un-used interrupts (Int no 139, 144, 145 and 146). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179582 MX6: Bypass PLL1 during WAITRanjani Vaidyanathan
When system is going to enter WAIT mode, set PLL1 to 24MHz so that ARM is running at 24MHz. This is a SW workaround for the WAIT mode issue. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-13ENGR00179631 MX6 SabreSD: Add MIPI DSI Display supportWayne Zou
Add MIPI DSI Display support on mx6 SabreSD board. MIPI DSI needs pll3_pfd_540M clock source for 540MHz. if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz. So add command line option disable_ldb when using MIPI DSI display. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-13ENGR00179628-2 MX6: add ssi info in sdmaGary Zhang
add ssi dual-fifo info in sdma structure Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-13ENGR00179621 MX6 PCIE: bring up PCIE on i.MX6 SD boardRichard Zhu
* Bring up the PCIE on i.MX6 SD board * Add the PCIE PHY access routines * Wrapper the board related codes by register one platform driver and data Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-04-13ENGR00179498-2 SDMA: fix p2p sdma script errorChen Liangjun
Update p2p script firmware address in plat-imx-dma.c for MX6Q. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-04-12ENGR00179284-2 support ONFI NAND device on mx6q_arm2_pop boardAllen Xu
enable ONFI NAND feature by command line parameter "onfi_support" Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-12ENGR00179497-2 MX6Q SabreSD: fix SPI nor flash pin configRobin Gong
Default SPI nor flash pin config is wrong, correct it for SabreSD RevB Signed-off-by: Robin Gong <B38343@freescale.com>
2012-04-11ENGR00177241-1 mx6 close APBH DMA clock when no I/O operationAllen Xu
When there is no NAND I/O operation, close all the reference clock, include GPMI,BCH and APBH clock. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-04-10ENGR00179129 Board support for I2C AMFM module for IMX6Q and IMX6DLAlejandro Sierra
Modifications in ARD board file to support the Audio for AMFM module for IMX6Q and IMX6DL (REV A and REV B) Supported for kernel 3.0.15. Also it contains the I2C configuration for the AMFM module. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-04-09ENGR00179135: workaroud for hung in flush_cache_user_range()Huang Shijie
This patch is from Russell King's email. It's just a workaroud for a known but not fixed issue, please read the following email: http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/073083.html The root cause of this bug is : "We cant be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock." Please read the email: http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/071708.html It seems from arm-v6, the cache flush can cause a page fault. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-04-06ENGR00178875-1 VDOA: Add vdoa support on i.MX6 SOC platformWayne Zou
Add vdoa support on i.MX6 SOC platform Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-06ENGR00177235-2 SDMA: add p2p dma modeChen Liangjun
Add code to support p2p dma mode.Add membership in imx_dma_data struct to support P2P dma script. Because the P2P dma script need 2 dma request to trigger DMA burst. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-04-06ARM: assembler.h: Add string declaration macroDave Martin
Declaring strings in assembler source involves a certain amount of tedious boilerplate code in order to annotate the resulting symbol correctly. Encapsulating this boilerplate in a macro should help to avoid some duplication and the occasional mistake. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-04-06ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflictsCatalin Marinas
This macro is used to generate unprivileged accesses (LDRT/STRT) to user space. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-04-06ENGR00178939 [mx6] usb host, msleep may be called in atomic contextTony LIU
- change msleep(1) to udelay(500) - msleep may be called in atomic context, which will cause warning message Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-04-05ENGR00178915: imx6 clock fix build warningsAdrian Alonso
* Fix build warnings * clock.c: In function '_clk_pll1_enable': warning: no return statement in function returning non-void * clock.c: In function 'mx6_clocks_init': warning: unused variable 'reg' Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-04-05ENGR00178951-2 SYSRQ: enable CONFIG_MAGIC_SYSRQ by defaultJason Liu
SYSRQ is very useful for kernel debug thus enable it by default. SYSRQ support serial port, we can send the command via minicom: CTRL A + F (send BRK) + T: to dump the task information Enable SYSRQ by default will not involve any performance drop Signed-off-by: Jason Liu <r64343@freescale.com>
2012-04-05ENGR00177581-4 MX6: add wm8962 mic supportGary Zhang
1. add amic_detect pin 2. add dmic_gpio init Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-04-05ENGR00160472 - MX6: add Ethernet ANSI/IEEE 802.2 LLC support in defconfig.Fugang Duan
- Add Ethernet ANSI/IEEE 802.2 LLC support. And the packet with IP head "ETH_P_802_2" will be processed in Ethernet stack L3 layer. - If disable the feature, ethernet stack will drop the LLC packets. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-04-05ENGR00178646-2 [MX6]Add SD1 and SD2 to interactive governorAnson Huang
Different have different SD ports, need to add all SD irqs to be condition of CPUfreq change and adjust the default irq threshold. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-04-04ENGR00175724-1 IPU: change ipu_device thread process mode to interrupt mode.Wayne Zou
IPU: change ipu_device thread process method to interrupt drive mode to get better IPU post-processing load balance. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-04-02ENGR00178763: MX6-Fix TO1.0 boot-fail issueRanjani Vaidyanathan
TO1.0 parts donot boot properly after the following commit: 88d3af87222b37e454acd6a8de3b0cf18180da32 MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz. Correct gpt_clk was not getting enabled. Fix by adding the appropriate gpt_clk. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-04-02ENGR00178584 uart3 pins configurationAlejandro Sierra
Uart 3 and NFC pins are shared. Uart 3 enablement is done by passing an early parameter called "uart3" from uboot. Both interfaces (Uart3 and NFC) can NOT coexist on the same configuration at the same time. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-04-01ENGR00178629 i.MX6 sabresd:support software power off by SNVS settingRobin Gong
On sabresd board, PMIC_ON_REQ control pmic power on/off, we can set TOP and DP_EN of SNVS_LPCR to implement power off by software. On this way,SNVS RTC alarm can work after power off. The description of register can be found on other SNVS block document which provided by IC team, not i.MX6 RM. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-03-30ENGR00178582 Remove uart2 early parameterAlejandro Sierra
UART2 and CAN interface do not have pins in common. Therefore uart2 early parameter is not required. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-03-30ENGR00178581 - EPDC fb: Fix regulator-related EPDC failure on SabreSDDanny Nold
Remove call to regulator_has_full_constraints() from Max17135 EPD PMIC initialization code, since leaving it enabled results in a failure of system to load properly - key regulators are disabled when 'epdc' is added to the kernel command line. Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-03-30ENGR00176366: MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz.Ranjani Vaidyanathan
PLL1 can be disabled whenever ARM_CLK is below 400MHz since ARM_CLK can be sourced from PLL2_PFD_400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-03-30ENGR00178552 MX6XX_SABRESD: update pin mux for revB board.Zhang Jiejing
update some pin mux of revB board. fix i2c3 not work on sabre6q board, and change related pins. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-03-30ENGR00178505 [MX6]Enable performance and ondemand governorAnson Huang
Enable performance and ondemand governor for CPUFreq, but default governor is still interactive. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-03-30ENGR00177932 - i.MX6 sabresd : Recorrect fec phy AR8031 rework.Fugang Duan
- i.MX6 sabresd board revA and revB adopt Atheros AR8031 phy. Recorrect the fec phy AR8031 rework. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-03-29ENGR00178458 - WM8962 regulator constraint fix to prevent unwanted disableDanny Nold
SPKVDD regulator was being disabled whenever EPDC was included in the image, because the EPD PMIC initialization code includes an invocation of regulator_has_full_constraints(). This causes all regulators with zero ref count to be disabled as part of a late_initcall. To prevent this disable (which breaks ethernet and DHCP), set regulator to have boot_on attribute, so that it will not be disabled at end of driver loading sequence. Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-03-30ENGR00178128 mx6 pcie: pass PCIEX1 CT network card verificationsRichard Zhu
what're done: * PCIE topology, RC should be on bus 0, EP should be on bus 1. Root Cause: The CLASS_REV of RC CFG header, specified by SPEC to be RO, should be set to PCI_CLASS_BRIDGE_PCIclass * Added PCIE PWR EN and RESET * iATU wrong configurations. Root Cause: The outbounds excepted the CFG region0 should be removed. Otherwise, the memory ATU wouldn't work correctly. * CT DHCP hang Root Cause: PLL8 is set to bypass mode when linux close fec, and the PCIe ref clk would be broken by PLL8 bypass mode. The parent clk of pcie ref clk is disabled by FEC, since linux would try to disable the none-addressed NIC after DHCP. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-03-28ENGR00178106 SabreSD: scan emmc slot sd4 firstly for mfgtoolsFrank Li
Mfgtools want to emmc block device node is fixed mmcblk0. Card in other slot is mmcblk1 or mmcblk2 Signed-off-by: Frank Li <Frank.Li@freescale.com>
2012-03-28ENGR00177875 mx6: pm: disable USB VBUS wakeup to avoid vbus wake systemPeter Chen
The USB VBUS wakeup should be disabled to avoid vbus wake system up wrongly due to vbus comparator is closed at weak 2p5 mode. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-03-28ENGR00177771 usb: usb wakeup enable should include both controller and phyPeter Chen
According to IC guys, it needs to enable/disable usb wakeup setting at controller and phy side together. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-03-27ENGR00178118-2 fix some build warnings when using GCC 4.6.2Jason Liu
fix some build warnings when using GCC 4.6.2: arch/arm/mach-mx6/board-mx6q_sabresd.c:1588:20: warning: function declaration isn't a prototype [-Wstrict-prototypes] This patch also fix the following section mismatch warnings: The function imx6q_init_audio() references the variable __initconst imx6_imx_ssi_data. This is often because imx6q_init_audio lacks a __initconst annotation or the annotation of imx6_imx_ssi_data is wrong. Signed-off-by: Jason Liu <r64343@freescale.com>
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