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On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz),
another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the
current cpu frequency is the highest set point(1G) or not to set the right
VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the
change point is the highest set point too. But there is three set points of
VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now
VDDSOC/VDDPU will track with VDDARM fully.
Signed-off-by: Robin Gong <B38343@freescale.com>
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For safety, DO NOT enable display power gating feature for MX6SL EVK.
Otherwise will meet PxP processing timeout when run EPDC unit test.
The cause is under investigation.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add enough nops to suspend code when exiting due to a pending
interrupt. This is required so that we can guarantee that the
prefetch unit will not bring DDR out of self-refresh before
all of the DDR's IO pads are restored.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to ensure that no page table walk occurs in DDR when it is in
self refresh and its IO pads are floated during suspend.
Hence we need to make sure that the translation of all the
addresses that the suspend code will access is in the TLB before
DDR cannot be accessed anymore.
So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters.
Also need to add a dsb to drain all the write buffers before
DDR enters self-refresh.
Also ensure that the LDO bypass enable is reset if an interrupt
is pending before the system enters suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Ensure that the transtion from low bus freq mode to
audio bus freq mode happens instantly. Don't schedule
the delayed work in this case else there will be a pause
in the audio playback.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix couple of race-conditions associated with low power IDLE code:
1. Ensure that bus freq mutex is used in the suspend/resume function
2. Ensure that the usecount of pll2 is incremented/decremented when
ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled
when necessary.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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There're two imx6q_add_ecspi() defines, remove one.
Signed-off-by: Robby Cai <R63905@freescale.com>
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- add imx6s_updater_defconfig to generate mx6sl firmware
- add CONFIG_MACH_MX6SL_EVK=y
- remove SMP for mx6sl
- add CONFIG_MX6_INTER_LDO_BYPASS=y
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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Need to ensure that check for usecount in clk_set_parent
occurs within the protection of the clock mutex. Else
there is a chance that the usecount can be decremented
(and the clock disabled) after the check.
Also add back the code to maintain the correct usecount
for pll2_pfd_400.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Ensure that the pull-up is enabled when the DQS line of LPDDR2
is floated when DDR freq is dropped to 24MHz. This is required
else its possible that the DDR will latch incorrect data when it
exits self-refresh.
CKE line should not be floated as it may cause DDR to incorrectly
exit self-refresh mode.
Also add 25 nops after the code that removes DDR from self-refresh.
We need this to ensure that the prefetcher block in A9 does not
access any instruction from DDR before the DDR exits self-refresh.
The A9 prefetch depth is about 23, hence 25 nops.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Make sure the Pull Ups are enabled on the DQS lines of
LPDDR2 memory. Without that its possible that the data
latched by the memory will be incorrect when exiting from
self-refresh mode. So only set the drive strengths to 0
when floating the DDR IO pads before entering suspend.
Also never float the CKE pad, this pin always needs to be
driven, else the DDR may incorrectly exit self-refresh.
Hence remove the line that was setting CKE drive strength
to zero (GRP_CTLDS).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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When system enter suspend, we increase CPUFreq to the highest point
without update the global loops_per_jiffy, it will lead to udelay
inaccurate during the last phase of suspend/resume.
WB counter and RBC counter need at least two 32K cycles to finish,
here we add 80us for safe.
Signed-off-by: Anson Huang <b20788@freescale.com>
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support adjust VDDSOC if enable LDO bypass on mx6_sabresd board
Signed-off-by: Robin Gong <B38343@freescale.com>
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Add port speed define MACRO to arc_otg.h.
Signed-off-by: make shi <b15407@freescale.com>
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For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after
the resume finished, otherwise, the remote-wake-up may fail. Because if the
device not switch to High-Speed 45ohm termination resistors mode, when the
disconnection detection bit is set the disconnection detection circuit will
detect a high speed disconnection by mistake.
Signed-off-by: make shi <b15407@freescale.com>
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We can't modify the usecount of pfd 400M clock when ARM freq
is changed, as when the children of pfd 400M do clock enable/disable,
they will also modify this usecount, these two modification is
out of same lock protection. And this wrong usecount may lead to
pfd 400M or pll2 disabled accidently, and it will cause system hang!
Signed-off-by: Anson Huang <b20788@freescale.com>
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1. Adjust ARM/SOC/PU voltage according to latest datasheet;
2. Remove Rigel's 200M setpoint to align with Arik.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The function has been implement in LDO enable , but not in LDO bypass.
Implement it on mx6sl.
Signed-off-by: Robin Gong <B38343@freescale.com>
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This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
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Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Checking of the bus_freq variables and changing of the
bus/ddr frequency should be done under one mutex.
Else there is a race-condition that the variable changed
just after it was checked.
Also ensure that the bus freq is always increased before
the cpu freq is set to anything other than the lowest setpoint.
Else there is a possibility that the ARM is set to run from
PLL1 at higher frequency when bus/DDR are still at 24MHz.
This is dangerous since when system enters WAIT mode in
low bus freq state, PLL1 is set to bypass when ARM is being
sourced from it.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add a new working point table to MX6SL and set the voltages
according to the latest datasheet.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add platform device for V4L2 support
Signed-off-by: Robby Cai <R63905@freescale.com>
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The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg vbus wakeup system will be supported
Signed-off-by: make shi <b15407@freescale.com>
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MSL headfile part change.
Signed-off-by: make shi <b15407@freescale.com>
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Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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[MX6X] Fix BogoMIPS value is not correct
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1.
Signed-off-by: Robby Cai <R63905@freescale.com>
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config audio pads to avoid pop-noise
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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[MX6SL]MMDC: DDR Controller's measure unit may return an incorrect
value when operating below 100 MHz
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
From schematic of ARM2 board, epdc and spi share this pin if plug epdc
daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
well firstly. So we make sure SPI-NOR work successfully by default. But if
enable epdc , SPI-NOR on ARM2 will work fail.
Signed-off-by: Robin Gong <B38343@freescale.com>
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- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
- Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
Signed-off-by: make shi <b15407@freescale.com>
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1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
3. Clear build warning.
Signed-off-by: Anson Huang <b20788@freescale.com>
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In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.
PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
by hw_anadig_ana_misc2_control0 bit.
Signed-off-by: make shi <b15407@freescale.com>
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The ENABLE bit is not set for all PLLs by default. Ensure
that the pll_enable() function sets this bit for all PLLs.
The pll_disable() function should not clear this bit
for PLL1, PLL2, PLL3 and PLL7. The output of these PLLs
maybe used even if they are bypassed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The problem is caused because the board init routine don't add the
corresponding device node. Problem resolved after add them
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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The problem is caused because "mx6_sabrelite_board_init" don't add the
corresponding device node. Problem resolved after add them.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Fix build break due to missing extern.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support for DDR freq change code in IRAM.
Change PLL2 to bypass mode so that DDR is running off 24MHz OSC
directly.
ARM is now sourced from PLL1 (running at 800MHz) in this mode.
This is required for the next step in IDLE mode optmization
where all PLLs will be disabled when ARM enters WFI.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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for avoiding pop-noise adn setting audmux pad to 1.8v on evk,
add pad ctrl for audmux iomux setting
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Original pad configuration does not provide enough bitfield width
to config some bits, such as LVE bit and DDR_SEL bits.
like gpr configuration, add a api to implement these special
bits pad configuration, and user may call this api in board file.
Signed-off-by: Gary Zhang <b13634@freescale.com>
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pdata->lowpower may be accessed at two drivers together, assumed
the situation that host/device set phy to low power mode but
still not set the flag lowpower, at this time the wakeup occurs, as
the flag lowpower is still not set, the interrupt will be infinite loop
as no one will serve it.
This commit is for MSL code and add protect at wakeup interrupt.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Keep the corresponding rail of pfuze: VGEN4 and VGEN1 "always on".
It's required for any IO pad configured as this voltage.
It has to be always on, even in DSM mode.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Adjust pfuse settings for wm8962
Signed-off-by: Gary Zhang <b13634@freescale.com>
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SOC/PU voltage need to following some rules according to latest
datasheet:
1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V;
2. SOC and PU must be same as they don't have level shift;
3. Adjust previous wrong voltage setting.
If SOC/PU voltage is too low, may cause system crash on some
chips, we have a board that easily crash with GPU working and
doing some tar operation, with this voltage adjust, this issue
fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix not able to set high bus frequency from low bus frequency.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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