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path: root/arch/mips/mm/pg-r4k.c
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2008-04-28[MIPS] Reimplement clear_page/copy_pageThiemo Seufer
Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12[MIPS] Fix loads of section missmatchesRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29[MIPS] R4000/R4400 daddiu erratum workaroundMaciej W. Rozycki
This complements the generic R4000/R4400 errata workaround code and adds bits for the daddiu problem. In most places it just modifies handwritten assembly code so that the assembler is allowed to use a temporary register as daddiu may now be treated as a macro that expands to a sequence of li and daddu. It is the AT register or, where AT is unavailable or used explicitly for another purpose, an explicitly-named register is selected, using the .set at=<reg> feature added recently to gas. This feature is only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the workaround remains disabled, the required version of binutils stays unchanged. Similarly, daddiu instructions put in branch delay slots in noreorder fragments are now taken out of them and the assembler is allowed to reorder them itself as possible (which it does making the whole idea of scheduling them into delay slots manually questionable). Also in the very few places where such a simple conversion was not possible, a handcoded longer sequence is implemented. Other than that there are changes to code responsible for building the TLB fault and page clear/copy handlers to avoid daddiu as appropriate. These are only effective if the erratum is verified to be present at the run time. Finally there is a trivial update to __delay(), because it uses daddiu in a branch delay slot. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] pg-r4k.c: Dump the generated codeMaciej W. Rozycki
Dump the generated code for clear/copy page calls like it is done for TLB fault handlers. Useful for debugging. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-03[MIPS] pg-r4k.c: Fix a typo in an R4600 v2 erratum workaroundMaciej W. Rozycki
Restore a load from KSEG1 done as a workaround for an R4600 v2 erratum, dropped with 211be16de99a7424e66c0b6c0d00e2c970508ac2. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-08[MIPS] TX49: Fix use of CDEX build_store_reg()Atsushi Nemoto
The commit a923660d786a53e78834b19062f7af2535f7f8ad accidently prevents TX49 from using CDEX. Use build_dst_pref() only if prefetch for store was really available. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-01[MIPS] 16K & 64K page size fixesRalf Baechle
Derived from Peter Watkins <treestem@gmail.com>'s work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01[MIPS] Treat R14000 like R10000.Kumba
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21[MIPS] TX49XX has prefetch.Atsushi Nemoto
The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!