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2014-07-24ARM:tegra:TN7: Correct gpio type for PK6 of fixed_regHarry Hong
Haven't seen any issue to control this gpio in TN7. however, correct it as it's correct. Change-Id: I4e1d63f62b6d0ef13d9c83941a741d89c8adf4b1 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/441694
2014-07-07ARM: tegra:TN7/TN7CW enable E2542 debug boardHarry Hong
if debug uart is set to 5, just mux sdcard mmc pins to UART-A. Bug 200018501 Change-Id: I22f05b38f772feb0483b1ce7c6fbbea85f884e3c Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/434972
2014-07-07arm: tegra: update Maxim touch AVDD rangedjung
Nvidia changes to update Maxim touch AVDD range. Bug 1522154 Bug 200006060 Bug 1522162 Bug 1444604 Bug 1493749 Change-Id: If8642c11a6e341cf011b1f01e3884512d067549f Signed-off-by: djung <djung@nvidia.com> Reviewed-on: http://git-master/r/427870 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-07-02USB: Phy: tegra: Enable POSTAMBLE_OUTPUT for HSICMartin Chi
As part of Phy power_on the POSTAMBLE_OUTPUT_ENABLE should be set for HSIC. Bug 200008073 Change-Id: I925cd632bcf5b1d10e5390c755d485adf623e745 Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/432201 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Gray Lei <glei@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
2014-06-25Revert "arm: tegra: Enable the ozwpan(USB HCD) driver"Kenneth Kwak
DO NOT INTEGRATE Bug 1466757 This reverts commit 8e486e05ceb575f9aa4cc3751e2ffebace09cf6b. Change-Id: I23ce80e1bdc64e2c7635a3f7b7eb72da9d15d240 Signed-off-by: Kenneth Kwak <kkwak@nvidia.com> Reviewed-on: http://git-master/r/428084 Reviewed-by: Peter Kim <pekim@nvidia.com> Tested-by: Peter Kim <pekim@nvidia.com>
2014-06-25Revert "arm: config: Enable NVIDIA hid driver"Kenneth Kwak
DO NOT INTEGRATE Bug 1466757 This reverts commit cf56f98a8147c0de6f6d393248d559054523a6d7. Change-Id: I8cde71bc6cf21408a21b182c49ce7b72ddb120a9 Signed-off-by: Kenneth Kwak <kkwak@nvidia.com> Reviewed-on: http://git-master/r/428073 GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Kim <pekim@nvidia.com>
2014-06-22Revert "mach: tegra: Increase touch avdd voltage TN7C/TN7"David Pu
This reverts commit 15f372c27c5c5803a3b129e9fd5bfdc791f701ba. Bug 200006060 Signed-off-by: djung <djung@nvidia.com> Signed-off-by: David Pu <dpu@nvidia.com> Change-Id: Id83812e5ee6bb2d12294b8b6c9bf0da7b0f8dbe4 Reviewed-on: http://git-master/r/423469 (cherry picked from commit efa282dc48a4c3a2437fa79d1767c357af8fd7ca) Reviewed-on: http://git-master/r/426233 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-06-17mach: tegra: set LDO4 as boot on.David Pu
LDO4 is turned on from bootloader to meet TS power on sequence. Bug 200006060 Change-Id: I2ad2fb5b287f9c66fdff7d4123dec2e1c7476e77 Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/419337 (cherry picked from commit 8540c6a74bb3a3efdb4507d0846a34d54d14f8c7) Reviewed-on: http://git-master/r/424447 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-06-17mach: tegra: set LDO4 as boot on.David Pu
LDO4 is turned on from bootloader to meet TS power on sequence. Bug 200006060 Change-Id: Ic5ece836d940e763da7c6a176bbe33efae6b706b Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/419977 (cherry picked from commit 737fe12882b78d0d515082fa8111e133d1163897) Reviewed-on: http://git-master/r/424452 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-06-15arm: dts: tegranote: cmu disable for dc1Min-wuk Lee
This will set change color correction preset for HDMI to Native in default. Bug 200012828 Change-Id: I7edb018da3a76aac3146627a76c7a7f48bfe3392 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/423141 GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-06-12arm: config: Enable NVIDIA hid driverKenneth Kwak
Enable NVIDIA hid driver for better gaming expereience on NVIDIA controllers, refering to http://git-master/r/#/c/339542/ Bug 1466757 Change-Id: Ibd5058af4afb28efdfe4915f92bef306e773a326 Signed-off-by: Kenneth Kwak <kkwak@nvidia.com> Reviewed-on: http://git-master/r/401211 Signed-off-by: Kenneth Kwak <kkwak@nvidia.com> Reviewed-on: http://git-master/r/417521 Reviewed-by: Peter Kim <pekim@nvidia.com> Tested-by: Peter Kim <pekim@nvidia.com>
2014-06-12arm: tegra: Enable the ozwpan(USB HCD) driverKenneth Kwak
Enable the ozwpan USB HCD driver via CONFIG_USB_WPAN_HCD. Make change manually based on http://git-master/r/328586 Bug 1466757 Change-Id: I3b3e9cb282c696171c6ca210b3060f13420770e3 Reviewed-on: http://git-master/r/401202 Signed-off-by: Kenneth Kwak <kkwak@nvidia.com> Reviewed-on: http://git-master/r/417512 Reviewed-by: Peter Kim <pekim@nvidia.com> Tested-by: Peter Kim <pekim@nvidia.com>
2014-06-09ARM:tegra:tn7cw: USB eye diagram calibrationHarry Hong
USB host/device mode eye diagram calibration host mode using +3 offset for XCVR setup parameter. device wiht no offset adjustment, but set bit[7:6] into 01 for slew rate calibration. Bug 1457966 Bug 1459798 Bug 200010446 Change-Id: Ieae4607d4bc51fa3aa83197318eaec04fd941a8f Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/421423
2014-06-09mach: tegra: Set touch avdd to 3.3V for TN7Harry Hong
Bug 1522162 Change-Id: I6d6c003dc45d451eed34838492105007380d09f3 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/421416 Reviewed-by: Automatic_Commit_Validation_User
2014-06-08arm:tegra:TN7CW: Add new DDR with ram-code=0b10Harry Hong
RAM_CODE[1:0]=0x00, Micron DDR3L, requires 1.38V RAM_CODE[1:0]=0x01, Hynix DDR3L, requires 1.35V RAM_CODE[1:0]=0x02, Micron DDR3L, requires 1.38V It's from http://git-master/r/#/c/418659/ Bug 1417014 Change-Id: I1bdc464023d94658e51fc415661c0f94e2935e5b Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/420451
2014-06-08ARM: dts: tn7cw: use tegranote7c-common.dtsiHarry Hong
Change-Id: I831d55efd3ecff9f88dfec8a55842f9e23203335 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/408673 (cherry picked from commit 212013c00c7b211c7ac3277903d88ddf3040d832) Reviewed-on: http://git-master/r/420397
2014-06-04arm:tegra:TN7C: Add new DDR with ram-code=0b10Martin Chi
RAM_CODE[1:0]=0x00, Micron DDR3L, requires 1.38V RAM_CODE[1:0]=0x01, Hynix DDR3L, requires 1.35V RAM_CODE[1:0]=0x02, Micron DDR3L, requires 1.38V bug 1417014 Change-Id: Id9e2137fd477c9af2b3a2e72ccf2b65c48b63d7e Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/418659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-06-04ARM: dts: tn7c: add new dvfs for Micron DDR3LMartin Chi
http://nvbugs/1417014/22 bug 1417014 Change-Id: Ic6db5a3d3bcb4bc193f59b94e46ca882196bd817 Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/418660 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2014-05-26ts: tn7 & tn7c: update touch regulatorNine Feng
1) Revert "ts :tn7c: support load switch for touch power rail" 2) Remove useless fix regulator: dvdd_ts and dvdd_lcd_1v8(which would cause lcd and touch use differnt supplies but same ldo4) 3) Enable avdd first Bug 200006060 Bug 1445143 This reverts commit 8b8d45d48da349159b2006202e13eea1bc652d51. Change-Id: I807a57ccb2828c53648be6189846a0d734d52e82 Signed-off-by: Nine Feng <nfeng@nvidia.com> Reviewed-on: http://git-master/r/414872 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-05-26ARM: tegra: HSIC: remove uhsic_phy_pre_resumeMartin Chi
during hub remote wake-up, uhsic_phy_pre_resume will be called to set RUN bit to end the 'Resume' signalling eariler than expected bug 1499837 Change-Id: Icf05fa78eb37f45e8b918ee0a01fa3ce5c038435 Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/414811 Reviewed-by: Gray Lei <glei@nvidia.com> Tested-by: Gray Lei <glei@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
2014-05-25usb: phy: tegra: Add usb_phy_reset for HSICBH Hsieh
usb_phy_reset was missing from uhsic_phy_ops hence USB_TXFILLTUNING kept incorrect value after ehci_reset then resulted in DataBufferErr on out endpoint Bug 200002033 Change-Id: I2942d22a12c45c9136f05841e36d839c1bd8fd86 Signed-off-by: BH Hsieh <bhsieh@nvidia.com> Reviewed-on: http://git-master/r/409288 (cherry picked from commit 0bef26360a617d41aece5f003b5972c39d082948) Reviewed-on: http://git-master/r/414122 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Martin Chi <mchi@nvidia.com>
2014-05-22ARM: tegra: tegratab: reduce fb0 mem sizeHarry Hong
reduce reserved mem size for fb0 according to lcd resolution. Bug 200002039 Change-Id: I6931d99ce7c62348c294b8de475e73d3554dfbfd Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/412527 (cherry-picked from d253cc10557628ddaf929d24fccfe4d47df3e040) Reviewed-on: http://git-master/r/413120
2014-05-19kernel: fairfax tskin parameterqtang
use tuned tskin parameter for fairfax device according to macro CONFIG_FAIRFAX_TSKIN bug 1482306 Change-Id: I2f686edc6f6377958724a329f579d0994b3ca508 Signed-off-by: qtang <qtang@nvidia.com> Reviewed-on: http://git-master/r/387644 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/404798 Reviewed-by: Tao Hu (SW-TEGRA) <taoh@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Tao Hu (SW-TEGRA) <taoh@nvidia.com> Reviewed-on: http://git-master/r/411239 Reviewed-by: Peter Kim <pekim@nvidia.com> Tested-by: Peter Kim <pekim@nvidia.com>
2014-05-18tn7c: modem: reduce autosuspend_delay to 1sMartin Chi
for power saving bug 200004582 Change-Id: I79bae98e82810be4472597cbe44dd3bf114cbbd1 Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/411167 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Gray Lei <glei@nvidia.com> Tested-by: Gray Lei <glei@nvidia.com>
2014-05-18Revert "usb: hsic: set sclk to 120MHz"Martin Chi
This reverts commit ad89889e50d13d43e4e58dcb79a8fc197a39422a. bug 200004582 Signed-off-by: Martin Chi <mchi@nvidia.com> Change-Id: I9bef43c07f2fdae6d0a55e987be7320edf944345 Reviewed-on: http://git-master/r/411165 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Gray Lei <glei@nvidia.com> Tested-by: Gray Lei <glei@nvidia.com>
2014-04-24ARM: tegra: Remove GPIO for HP form LP0 wake listLei Fan
Remove a GPIO for headset detection form the list of LP0 wake source Bug 1499477 Change-Id: Ie0331079072f2976265d5db1483cd905f0c1f2bc Signed-off-by: Lei Fan <leif@nvidia.com> Reviewed-on: http://git-master/r/396879 Reviewed-by: Vijay Mali <vmali@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Martin Chi <mchi@nvidia.com>
2014-04-23ARM: tegra: tn7cw: update tskin coeffcientsHarry Hong
Bug 1502030 Change-Id: I48587826212a670b694801b704907bfb8e2f051c Signed-off-by: Harry Hong <hhong@nvidia.com> (cherry-picked from 1641e1a29e2590d9cbcd29dad6fc16be42c48f29) Reviewed-on: http://git-master/r/400070 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yong Goo Yi <yyi@nvidia.com> Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-04-21ARM: tegra: power: Add read fences in power gatingAlex Frid
To assure post of the previous writes through Tegra interconnect added read fences in the following power gating code paths: - Seconadry CPU boot ungating (path taken on Tegra11) - MC client ungating flush done (path taken on all platforms) Bug 1484343 Change-Id: Ie09ef37135beae0ed0beb1cd4d7e96187ba9be26 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/385403 (cherry picked from commit 28b107dcb3aa122de8e94e48af548140d519298f) Reviewed-on: http://git-master/r/396764 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-04-21ARM: Tegra: Fix PowerGate status logicBhavesh Parekh
In the code we are reading value of PMC_PWRGATE_TOGGLE in reg variable. But loop was checking for status variable. Fix the same Bug 1479800 Change-Id: If18bf9ddcb403b60f084dee2edf3980e06ff2e3b Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com> Reviewed-on: http://git-master/r/309991 (cherry picked from commit 095ba8e09b545222fdd343f9c65692057eb7bb29) Reviewed-on: http://git-master/r/396763 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-04-21arm: tegra: fix clamp status maskPrashant Gaikwad
PCIE and VDE ids are swapped in REMOVE_CLAMPING_COMMAND but not in CLAMP_STATUS. This results in timeout for VDE partition. Bug 1390084 Change-Id: I5d14688f7140d9fc23bb54798147620f631402d1 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/300346 (cherry picked from commit 27e082ce29fa0cdcbbb3fc2991dd21e045f429d3) Reviewed-on: http://git-master/r/396762 Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-04-21arm: tegra: make sure that the PG request is accepted by PMCPrashant Gaikwad
The role of START bit has changed, beginning T35. To account for bug 863229 start bit will now be cleared by HW when PMC accepts the request to powergate or unpowergate the partition. So in order to powergate/unpowergate a partition SW needs to do the following. 1. Check to see if the partition is already in the correct state, by looking at the PWRGATE_STATUS register. If not then SW reads the PWRGATE_TOGGLE register to see if START bit is 0. If not poll till start bit is set to 0. 2. After that program the PWRGATE_TOGGLE register with start bit set as 1 and choose the required partition to be powrgated. 3. Ideally then SW can poll to check the START bit going back to 0, to indicate that PMC has accepted the request. 4. Then poll the STATUS register to make sure the required partition is powergated/unpowergated. Also, in current implementation SW is polling REMOVE_CLAMPING_CMD to check the CLAMP remove status. As per the HW guys this register is write only and does no make sense polling it. Instead use CLAMP_STATUS for polling. Bug 1376147 Change-Id: Id34e900dff870d4d22288922ee1d0487ab4911dc Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/299801 (cherry picked from commit 7f36693c47cb23730a6b2822e0975be65fb0c51d) Reviewed-on: http://git-master/r/396761 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> Tested-by: Min-wuk Lee <mlee@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-04-17mach: tegra: Set touch avdd to 3.0V for TN7Harry Hong
Bug 1478633 Bug 1493749 Change-Id: I321483744a93d96b604c36d65bec4b3d8e84d089 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/398061 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yong Goo Yi <yyi@nvidia.com>
2014-04-15kernel:camera:set ov7695 brightness as +2qtang
Bug 1461802 Change-Id: Ic49106b81775e5b29bd4db9d453b164ad3f5010c Signed-off-by: qtang <qtang@nvidia.com> Reviewed-on: http://git-master/r/387619 GVS: Gerrit_Virtual_Submit Reviewed-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/395656 Reviewed-by: Tao Hu (SW-TEGRA) <taoh@nvidia.com> Tested-by: Tao Hu (SW-TEGRA) <taoh@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-04-13ARM: tegra: HSIC: Clear PD_TX during resumeSuresh Mangipudi
During HSIC resume the PD_TX circuit is to be turned on before clearing MASTER_ENABLE of PMC. Bug 1491453 Change-Id: I26c30fc241f638411b94f45b28f155b4eeabdaea Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-on: http://git-master/r/395076 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Martin Chi <mchi@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Martin Chi <mchi@nvidia.com>
2014-04-08mach: tegra: Increase touch avdd voltage TN7C/TN7Robert Collins
Increase touch AVDD voltage for TegraNote TN7 and TN7C. Bug 1478633 Bug 1493749 Change-Id: Id07da3f101ee8f2d42abf5ba0a2d1487bafdec6f Signed-off-by: Robert Collins <rcollins@nvidia.com> Reviewed-on: http://git-master/r/392032 (cherry picked from commit 15f372c27c5c5803a3b129e9fd5bfdc791f701ba) Signed-off-by: David Jung <djung@nvidia.com> Reviewed-on: http://git-master/r/392137 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Kim <bok@nvidia.com> Reviewed-by: Youngjin Kim <nkim@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-04-07ARM: tegratab: config: make mpu & akm modulesDavid Yu
Bug 1491475 Change-Id: Id5e78b62202d3392911aeb2f9ab820fac50f8969 Signed-off-by: David Yu <davyu@nvidia.com> Reviewed-on: http://git-master/r/392788 Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-04-06ARM: tegratab: config: clean up configsDavid Yu
Remove unused baseband configs Remove unused BCM configs Remove unused NFC configs / Add NXP PN533 USB NFC driver Remove unused RTC configs Remove unused touchscreen configs Move MPU and AKM from modules to static binary Bug 1491475 Change-Id: I53d1ef8362ca70aebd3f7afd2faa3516b6e1b06c Signed-off-by: David Yu <davyu@nvidia.com> Reviewed-on: http://git-master/r/392232 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-26tegra:fairfax: Disable EDPericz
Disable EDP for HP's request. Change-Id: I438f0248a747f1f5bc9ab6c9bd6ebf956a0daf28 Signed-off-by: ericz <ericz@nvidia.com> Reviewed-on: http://git-master/r/385508 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Simon Je <sje@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-20ARM: dts: tegranote: reduce charger mode brightnessHyong Bin Kim
For safety, reduce charge mode display value. Bug 1470109 Change-Id: Iab1e11871ba82fc0cdd7b8889c0fee3087f1a3fc Signed-off-by: Hyong Bin Kim <hyongbink@nvidia.com> Reviewed-on: http://git-master/r/383888 Reviewed-by: Min-wuk Lee <mlee@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-20ARM: tegra: tn7c: runtime select tskin coeffcientsNine Feng
Bug 1468114 Bug 1432052 Change-Id: I534295b63540d3a5604d92f9f5f3c7237edfec77 Signed-off-by: Nine Feng <nfeng@nvidia.com> Reviewed-on: http://git-master/r/380377 Reviewed-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Danny Song <dsong@nvidia.com>
2014-03-19ARM: tegra: usb: set usb.emc back to 100MHzHarry Hong
Set usb.emc 100MHz but if type is HSIC, remain to 200MHz Bug 1466876 Change-Id: I9933090ab33e7ab7e394bdf53607d0a2707e99d1 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/383802 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hyong Bin Kim <hyongbink@nvidia.com> Tested-by: Hyong Bin Kim <hyongbink@nvidia.com> Reviewed-by: Martin Chi <mchi@nvidia.com>
2014-03-18arm: tegra: tegratab: fix more P1988 gyro pinmuxDavid Yu
Bug 1482346 Change-Id: I44b56956441f38416aee7a986229707687e27d6f Signed-off-by: David Yu <davyu@nvidia.com> Reviewed-on: http://git-master/r/383138 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-18arm: tegra: tegratab: fix P1988 gyro pinmuxDavid Yu
Bug 1482346 Change-Id: I7472fb40f93833196af9969c08d62466dcc6d31f Signed-off-by: David Yu <davyu@nvidia.com> Reviewed-on: http://git-master/r/382838 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Harry Hong <hhong@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-17ARM: tegra: tegratab: add p1988 skin_dataHarry Hong
Bug 1439626 Change-Id: Iff23da5367b426ade1875f50cf5a3bdfa4441544 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/382407 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yong Goo Yi <yyi@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-03-17ARM: Tegra: TN7C: correct the pin usageMartin Chi
On TN7C, these pins has nothing to do with codec. They are actually connecting to modem as: TEGRA_GPIO_PP3 --> AP_WAKE_MDM TEGRA_GPIO_PP1 --> W_DISABLE_N Change-Id: I509c3ce017036f2cd3e2d72a08a23605fd73084d Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/382441 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Lei Fan <leif@nvidia.com> Tested-by: Lei Fan <leif@nvidia.com> Reviewed-by: David Pu <dpu@nvidia.com> Reviewed-by: Gray Lei <glei@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-03-17dts: tn7_2014: update dts for latest settingHarry Hong
Bug 1438727 Change-Id: I4aa2c704e3223352f26834bee172116d151d75e4 Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/382396 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Danny Song <dsong@nvidia.com>
2014-03-16ARM: tegra11: clock: Use exact PLL rate in resumeAlex Frid
Removed 1Hz margin from target rate request during PLL resume. Although the PLL output rate is restored correctly in any case, PLL dividers settings may differ from tabulated targets (if any) when non exact rate is requested. Bug 1473597 Change-Id: I5307ee49fcac4ce6dc6b3c38d1841629060700d7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/379620 (cherry-picked from 96a02b52db51498756967864d9c5a3596f812570) Reviewed-on: http://git-master/r/381927 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Pu <dpu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com>
2014-03-14arm:tegra:TN7:set SMPS6 active mode to Force PWM.David Pu
it is sw WAR to fix screen flicker when charging. Bug 1480539 Bug 1475028 Bug 1480536 Change-Id: I0115aec93149997cf6f10ba1b4a740427eddbdba Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/381897 Reviewed-by: Yong Goo Yi <yyi@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com>
2014-03-13arm:tegra:TN7C:set SMPS6 active mode to Force PWM.David Pu
it is sw WAR to fix screen flicker when charging. Bug 1475028 Bug 1480536 Change-Id: I3cf660157d34b4e8ebdd6235cc38c86ea9210657 Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/381329 Reviewed-by: Martin Chi <mchi@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yong Goo Yi <yyi@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Danny Song <dsong@nvidia.com>
2014-03-12usb: hsic: add delay in phy resume for auto-resumeMartin Chi
add 10ms delay in hsic phy resume for auto-resume bug 1476774 Change-Id: I54d0b46347084b3e41520f4c0f878a1336b54931 Signed-off-by: Martin Chi <mchi@nvidia.com> Reviewed-on: http://git-master/r/380736 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gray Lei <glei@nvidia.com> GVS: Gerrit_Virtual_Submit
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-29 18:54:00 +0000