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Bug 922351
Reviewed-on: http://git-master/r/78310
Change-Id: I4d1a341386b10c584715d2bbb76ac69877b47fb7
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78904
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Do not use common lp2 exit latency for Tegra3 secondary CPUs in
G mode. Separately measure and adjust latency on each slave CPU;
use per-cpu latency to determine target residency threshold for
entering lp2 on each CPU.
Reviewed-on: http://git-master/r/78375
Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78903
Reviewed-by: Automatic_Commit_Validation_User
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Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes.
Separately measure and adjust latency in each mode; restart calculation
after mode switch from the last measured latency in the target mode.
Reviewed-on: http://git-master/r/78344
Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78902
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Change vi and vi/isp source from PLLM to PLLP.
It saves power by shutting down PLLM in low emc bandwidth use
case.
Bug 923794
Reviewed-on: http://git-master/r/78224
Change-Id: I39b051a5169b76f06bce9b99f80b0b50c0d3f1bf
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78901
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.
Reviewed-on: http://git-master/r/77957
Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78899
Reviewed-by: Automatic_Commit_Validation_User
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Move Tegra GIC initialization to be with the other GIC functions.
Change-Id: I9b23757d135f3a9062f21fccb816c745ce8add43
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/78829
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Fuse registers are made visible during init.
As they need not be masked and unmasked during
every fuse access, removing these functions.
bug 933113
Reviewed-on: http://git-master/r/78355
Change-Id: If95c021b9ec377ba9610eedd481ec3c8ff6bf874
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78714
Reviewed-by: Automatic_Commit_Validation_User
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Fixed linux warnings in baseband_xmm_power.c file.
BUG 921565
Reviewed-on: http://git-master/r/77964
Change-Id: I6d0c6ef0c30351d6bfc77a733d306ab581ad9ea6
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78712
Reviewed-by: Automatic_Commit_Validation_User
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Disabling USB3 for whistler as it is not a typical
use case.
Bug 872683
Reviewed-on: http://git-master/r/78197
Change-Id: I0c70ceb68717277e892758ce1742e52a99a7f0da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78711
Reviewed-by: Automatic_Commit_Validation_User
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If there is PMU interrupt for device mode set is_dpd
to true. This will disable avdd_usb regulator.
Bug 926694
Reviewed-on: http://git-master/r/78196
Change-Id: I7e0045ecb53f2fc984d567ff0e1331620f61be1d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78710
Reviewed-by: Automatic_Commit_Validation_User
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Added new tables for T37/T33A (same table as T33) and AP37
Bug 844268
Reviewed-on: http://git-master/r/77662
Change-Id: I51e0939eb2f1f5582215bc409cf2d8eaf9890fba
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78709
Reviewed-by: Automatic_Commit_Validation_User
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- Detect T37 and AP37 SKUs.
- Created a new threshold for T37
Bug 841336
Reviewed-on: http://git-master/r/77661
Change-Id: I78a6875058ebd6bc5e70042aec020c259de0976c
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78708
Reviewed-by: Automatic_Commit_Validation_User
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- Added Tegra3 x7 core dvfs entries
- Increased EMC, graphics, and UART clocks maximum limits
- Updated PLLC configuration table
Bug 841336
Reviewed-on: http://git-master/r/76942
Change-Id: Ifa235e60d66d959ad589574c5ebde90eb0b65385
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78707
Reviewed-by: Automatic_Commit_Validation_User
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Bug 841336
Reviewed-on: http://git-master/r/76912
Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78706
Reviewed-by: Automatic_Commit_Validation_User
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Use platform_device_add_data() instead of kmalloc for creating
a copy of platform data. Let the driver-model release the memory
allocated for platform_data to avoid possible memory leak.
Bug 923597
Reviewed-on: http://git-master/r/77544
Change-Id: Ic7a54e773c95999b14ec97059a2f49999ea7d5ed
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78705
Reviewed-by: Automatic_Commit_Validation_User
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- Completely removed PLLP restoration from CPU complex resume on
Tegra3 platforms (too late: if necessary PLLP is restored by LPx
exit code on Tegra3, and attempt to restore it again does not do
any good).
- Restored PLLX only if it is not already used as CPU source
(it is dangerous to restore PLL in use).
- Restore burst policy on exit from LPx states, but preserve it
after cluster switch, as it maybe different for LP and G clusters.
Reviewed-on: http://git-master/r/72535
Change-Id: Ia5ff24d22a2135494bc3442f92bebcc1953c7f08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78702
Reviewed-by: Automatic_Commit_Validation_User
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Verbier PM269 of cardhu builds do not contain INA219 components
to monitor power. Stopping drivers from loading on PM269 to remove
i2c error prints.
Bug 927866
Reviewed-on: http://git-master/r/76704
Change-Id: I7a20a9942da58e1d18e75719b43be86ecc2ded01
Signed-off-by: Gary Fitzer <gfitzer@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78699
Reviewed-by: Automatic_Commit_Validation_User
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Replaced iovmm_align_{up,down} with round_{up,down}
Reviewed-on: http://git-master/r/66369
Change-Id: Ie0e2b8b97c57ae3addcfe63968d00f6937cbc7d8
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78698
Reviewed-by: Automatic_Commit_Validation_User
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Properly report LP3 state to idle governor when LP2 entry is not
allowed and LP2 request is redirected to LP3.
Reviewed-on: http://git-master/r/77956
Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78697
Reviewed-by: Automatic_Commit_Validation_User
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enable CONFIG_NFC and CONFIG_PN544_NFC to support pn544.
Bug 932798
Change-Id: I411edc7dbf97afd050cfe4f68991a2f132886773
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/78689
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Pass wakeup_enable = true through platform data for interrupt
keys to enable wakeup functionality from suspend states.
Change-Id: I5d58bb0ed34991ca429dbd6f4c2448782c343dbf
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78608
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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bug 925600
Change-Id: I2560a0874f5af96a8f59922ab0f267c676662ca1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78606
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/77830
Change-Id: If1fbb73eff40dafdb7bcbe8da451115ef2105b0b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78441
Reviewed-by: Automatic_Commit_Validation_User
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Check error returned by cpufreq table helper API to avoid using
uninitialized table index in failed case.
Reviewed-on: http://git-master/r/77523
Change-Id: Ie47481a27397c6cafe73bfbddab0a392837ad019
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78439
Reviewed-by: Automatic_Commit_Validation_User
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1) Enable TEGRA_GPIO_PU0 for Bluetooth
2) Add platform device wl128x_device and btwilink_device for Bluetooth
3) Set platform data kai_wlan_data for WiFi
Bug 926128
Reviewed-on: http://git-master/r/75929
Change-Id: I3bbe48899358106a299728e924e5a893f68ac60c
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78437
Reviewed-by: Automatic_Commit_Validation_User
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Bug 926128
Reviewed-on: http://git-master/r/75252
Change-Id: I7f9928ab1efdb82ab73eea595c2a8590057b8c72
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78436
Reviewed-by: Automatic_Commit_Validation_User
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baseband_xmm_power driver is updated with suspend/resume noirq callbacks.
If any CP wake-up is pending during suspen_noirq callback, then ongoing
system suspend will be aborted. With this mechanism, CP wakeup after
baseband_xmm_power driver suspend is handled.
BUG 904762
Reviewed-on: http://git-master/r/72933
Change-Id: Iae6f638885118c73d6154aad9daefee0cfc8e7d4
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78435
Reviewed-by: Automatic_Commit_Validation_User
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Expand PLL usage restriction mechanism from Tegra3 only to common
tegra clock framework implementation: fail set parent API if new
parent is not allowed per usage policy.
Actual usage policy is architecture dependent and exists now only
on Tegra3.
Reviewed-on: http://git-master/r/77251
Change-Id: I2a8d60cc0ddfd2179961ef50418b193f2e1829c8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78029
Reviewed-by: Automatic_Commit_Validation_User
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Check PLL usage policy when traversing clock tree for descendants of
sleeping clock. Don't propagate cansleep attribute if parent is not
allowed.
Reviewed-on: http://git-master/r/77252
Change-Id: Ibe79888d378924f416f8458146b21d1bc3671f16
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78028
Reviewed-by: Automatic_Commit_Validation_User
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Configure wake irq for waking up AP from xmm modem.
Also enable/disable this wake source base on flight mode
off/on setting.
Reviewed-on: http://git-master/r/69701
Change-Id: Iad274da9869102874efab27312fe8a182ab55bf3
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78026
Reviewed-by: Automatic_Commit_Validation_User
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Increasing timeout to 25ms for bus connect and bus idle.
New bus_reset times out for the first time, fix this by
changing USB phy mode to HSIC.
Bug 922444
Reviewed-on: http://git-master/r/73367
Change-Id: I717c98a4e3e8d943a8a922c70442211a0f7fd9be
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78017
Reviewed-by: Automatic_Commit_Validation_User
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The functon tegra_dma_dequeue() duplicates the functionality
of tegra_dma_dequeue_req().And this function does not use proper
locking before accessing the channel data.
Removing this function.
Change-Id: Ib6baaa984b038908c49adb3a0f3df3433f0a9066
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77805
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Dma user must call the function tegra_dma_get_transfer_count()
for knowing transferred count without stopping dma.
Change-Id: I5e0060fd8163b285496442268548a90bdd0e294c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77800
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Enable Snaptics SPI touch driver which is used for DirectTouch
purposes.
bug 912775
Reviewed-on: http://git-master/r/76379
Change-Id: I2a2bc4dd68c09039dd36b6c8786b8d16ecb35c80
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77776
Reviewed-by: Automatic_Commit_Validation_User
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android-tegra-nv-3.1
Change-Id: I9001bb291779f107bbcb593d48f9f0f734074d0e
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Add 51 MHz entry to cpufreq tables (102 MHz was minimum supported
rate before).
Bug 922351
Reviewed-on: http://git-master/r/77511
Change-Id: I20eea30cdadfb9efbf6489f8aaf5934f653af128
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78032
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Set CPU rate floor to 100MHz when the system is awake (after boot,
or on late resume). Remove the floor when the system enters early
suspend.
Bug 922351
Reviewed-on: http://git-master/r/77444
Change-Id: I68f54a3d981c1cbeac16d58d3beb6e3aa6bf190c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78031
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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On Tegra3 PLLC should be used as a parent clock only for graphics bus
(cbus) modules and secondary PLLC divider. Fail set parent API if PLLC
is selected as a new parent for other clocks.
Reviewed-on: http://git-master/r/77253
Change-Id: I564278dcdd62c17c6446218955c366b1612c73b3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78030
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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bug 871603
Reviewed-on: http://git-master/r/72258
Change-Id: I2ff63550fde536ee0e0f1b69b3a58e4f164e62e5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78027
Reviewed-by: Automatic_Commit_Validation_User
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Don't check if an unsigned variable < 0.
Reviewed-on: http://git-master/r/77466
Change-Id: Ia61781a8f5b8ebcdc39501486ed3f893a91d3430
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78015
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/77405
Change-Id: Ia77147074cb90d0ed22f64135a16b374f258b008
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78013
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/77400
Change-Id: Idbc213bb17d0e006c9a4cdaf500a94dbae1007d0
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78011
Reviewed-by: Automatic_Commit_Validation_User
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Change the minimal rate of sclk to 12 MHz and set the lowest
frequency of sbus to be 40 MHz when display is on.
BUG 922351
Reviewed-on: http://git-master/r/76959
Change-Id: I6a2871d1cc02a19829cf397e9583122e02255f81
Signed-off-by: Wen Yi <wyi@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78010
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Added touch setup and init calls to board-kai.c & h files
Also limited max spi clock rate (sbc1) to 72 Mhz
Bug 912775
Bug 832605
Reviewed-on: http://git-master/r/76402
Change-Id: I616bd97538c1513307bce178bb9fd4040a9ecd4d
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77777
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Board file for Synaptics SPI touch connection which is
used for DirectTouch initialization
Bug 912775
Reviewed-on: http://git-master/r/74643
Change-Id: Ie296ddff5b9e1fbf9296d40fde2877598a13207e
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77775
Reviewed-by: Automatic_Commit_Validation_User
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Board file for Raydium SPI touch connection which is
used for DirectTouch initialization
Bug 832605
Reviewed-on: http://git-master/r/74618
Change-Id: Icac5ebd22b5a3b6fe38d3e23a37f88df067c0c10
Signed-off-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77773
Reviewed-by: Automatic_Commit_Validation_User
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Added Tegra3 MSelect clock to memory on CPU clock dependencies:
MSelect rate is scaled as half of CPU rate, up to 102MHz. Prevented
CPU clock increase if updates of dependent clocks (EMC and MSelect)
have failed.
Reviewed-on: http://git-master/r/76485
Change-Id: I679b60eb5aa13d5cca2b9751ff2c8c2fb866a076
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77767
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Added clock for memory path selection module (MSelect) to Tegra3
peripheral clocks. Initialized MSelect clock rate to 102MHz.
Reviewed-on: http://git-master/r/76484
Change-Id: I73676882d8e6805445985b23257bcf6410e8c3e0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77766
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Re-enable usb auto suspend on system resume by making
get_interface() and put_interface() calls.
BUG 921565
Reviewed-on: http://git-master/r/73468
Change-Id: Ieb7c82e73a7134e1d3bb8b0b3e96a42ed6672afe
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77763
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Reviewed-on: http://git-master/r/77216
Change-Id: I1a9183102bcb1c70956f773101b2cf78c4dc2fc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77758
Reviewed-by: Automatic_Commit_Validation_User
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