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2012-10-11tegra: colibri_t30: add more video modesMarcel Ziswiler
Add the following tested (e.g. framebuffer console and X) video modes: - 800x480@60 (e.g. for EDT ET070080DH6) - 800x600@60 - 1024x768@60 - 1024x768@75 - 1280x720@60 aka 720p - 1366x768@60 The define TEGRA_FB_VGA in board-colibri_t30.h can be used to switch between VGA and 800x480.
2012-10-10colibri_t30: fix touch interrupt and tune touch responsivenessMarcel Ziswiler
Enable touch interrupt GPIO and tune STMPE811 platform parameters for better touch responsiveness.
2012-10-10ARM: tegra: ventana: disable usb1 vbus gpioPreetham Chandru R
disable the usb1 vbus gpio in kernel and not depend on bootloader to disable the vbus initially. Currently, the kernel enables and disables the vbus when the otg is configured to host mode, but when the system boots with no cable connected the kernel relies on the bootloader to turn the vbus off. This CL removes that dependency. Bug 1047048 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: http://git-master/r/#change,141970 (cherry picked from commit c3461995dd156968d766ec05879fd1097221ceb8) Change-Id: I96c1f4b97a2cafdfd498b591647200d26298a43b Reviewed-on: http://git-master/r/142839 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kiran Adduri <kadduri@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-10-04enabling P2P for bcmdhd driverMursalin Akon
Bug 1029792 Change-Id: I8ee7190ccd50863f6f0f1aa216035afbae57ebcf Signed-off-by: Mursalin Akon <makon@nvidia.com> Reviewed-on: http://git-master/r/141631 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro <mapedro@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-10-04config: use CFG80211 for bcmdhdMursalin Akon
CFG80211 is needed for WFD. So, use CFG80211, instead of, WEXT in bcmdhd driver. Bug 1029792 Bug 1029733 Change-Id: I81d99a821429f3be8400355faa5bee14904c0944 Signed-off-by: Mursalin Akon <makon@nvidia.com> Reviewed-on: http://git-master/r/141630 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro <mapedro@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-10-03asoc: colibri_t30: initial sgtl5000 codec integrationMarcel Ziswiler
Integrate ALSA SoC SGTL5000 codec on Toradex Colibri T30.
2012-10-03tegra: colibri_t30: hack to avoid clock warningsMarcel Ziswiler
Hack to avoid extensive warnings being logged during boot-up due to CPU clock adjustments before regulator being ready.
2012-10-03tegra: colibri_t30: initial Toradex Colibri T30 L4T R16 supportMarcel Ziswiler
Tested on early prototype Colibri T30 V1.0a eMMC module. Known issues: - spurious boot hang after following kernel message [ 5.595219] Timed out waiting for lock bit on pll pll_a - no audio (SGTL5000) support integrated yet - NAND detection/support disabled for now due to boot hang - USB OTG support disabled for now due to boot hang - trying to spawn L4T R16 X driver seems to hang Note: requires uImage with adjusted entry point/load address as follows mkimage -A arm -C none -O linux -T kernel -a 0x82008000 -e 0x82008000 -n 'Linux-3.1.10-colibri_t30' -d zImage uImage
2012-10-03tegra: colibri_t20: clock clean-upMarcel Ziswiler
Clean-up some of the early clock initialisation hacks.
2012-10-02tegra: colibri_t20: add more video modesMarcel Ziswiler
Add the following tested (e.g. framebuffer console and X) video modes: - 800x480@60 (e.g. for EDT ET070080DH6) - 800x600@60 - 1024x768@60 - 1024x768@75 - 1280x720@70 aka 720p - 1366x768@60 The define TEGRA_FB_VGA in board-colibri_t20.h can be used to switch between VGA and 800x480.
2012-10-01arm: tegra: cardhu: Reserve 16MB on RAM for HDMIShashank Sharma
Reserve 16MB for HDMI maximum possible resolution (1920x1080) at 32 bpp and double buffering. Change-Id: Id719a875b805723758485f970ab9e2f1a28ed19b Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/121562 (cherry picked from commit d376bc491a460353124adc0f2be8612add0d8e76) Reviewed-on: http://git-master/r/140032 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2012-10-01ARM: tegra: fix-up tegra_gpio enable/diablse defsMatt Pedro
Clean-up the definition of the tegra_gpio enable/disable so that it compares to the l4t r16 rel. Change-Id: Ia8584ada1e2a728d2784d6d57c72ed4b0ee01cf1 Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/140648 Reviewed-by: Automatic_Commit_Validation_User
2012-10-01tegra: colibri_t20: fix pwm backlightMarcel Ziswiler
Fix PWM backlight by using PWM<A> rather than PWM<C> by default. Invert brightness value due to unified TFT interface displays (e.g. EDT ET070080DH6) inverted LEDCTRL pin behaviour (e.g. 0V brightest vs. 3.3V darkest) and use PWM frequency of 1 kHz as recommended. Add comment about PWM pin muxing. While at it do some ifdef and indentation clean-up.
2012-10-01tegra: fix usb_phy build breakage if gadget as moduleMarcel Ziswiler
Add missing symbol exports to address gcc 4.7.2 from oe-core throwing following errors if usb gadget stuff compiled as modules (cf. 328d61af72a8f59f5dc53db8cddf8c8e572ad958).
2012-09-30ARM: tegra: fix-up definition by adding 'static'Matt Pedro
Fix up the definition of the tegra_gpio enable/disable. Change-Id: Id71242690efa3e5994a4b70089826f2b87997ece Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/140036 Reviewed-by: Automatic_Commit_Validation_User
2012-09-30ARM: tegra: Fix missing functions in gpio headerMatt Pedro
Fix the missing tegra_gpio enable/disable function defitintions. Change-Id: I82ed085bd67486d5e9c383a8c26243e2c1edf670 Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/140026 Reviewed-by: Automatic_Commit_Validation_User
2012-09-17arm: tegra: raise cpu floor when display is onWen Yi
When device is idle and display is on, the minimal cpu frequency can drop to 51mhz. Since it takes several tens of millisecond to ramp up cpu freq, the delay impact negatively the performance of low latency CPU bound tasks. Given the power savings of several milliwatts running cpu at 51mhz comparing to 102mhz or 204 mhz at idle, the idle cpu freq is hence raised to 102mhz for smart panel device and 204mhz for dump panel devices. Bug 1036216 Change-Id: Ifb0ed88d4c5fcf5b637d09c587322cec72b8a08d Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit c8465feffcd0cf2401bbd6c6f535955dd68bda55) Reviewed-on: http://git-master/r/132479 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ujjaval Patel <upatel@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-13arm: tegra: usb_phy: set vbus_reg to NULLPetlozu Pravareshwar
Setting vbus_reg to NULL if regulator get fails. Bug 1047065 Change-Id: I574f58d46f226d70034a4f363103fd9763482292 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: http://git-master/r/131759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-09-11Revert "ARM: tegra: cardhu: set I2S as slave mode"Sumit Bhattacharya
This reverts commit 616ade39df296b2c60d8ce74c719bc560f78f598. Bug 1046372 Change-Id: I1e8554f773e6af459f50658b683eafb2b0160f64 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/131458 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-09-10WAR: gr3d: limit 3d clock when camera is onJihoon Bang
As WAR, limit 3d clock frequency and emc clock frequency when camera is on and chip is AP37. 3d clock is set to 361MHz and 437MHz is requested for emc clock with this change. This change allows 3d to request 1.1V in Core instead of 1.3V in AP37. Bug 1001262 Bug 1019309 Change-Id: I9f46f93d8da0fcf5afe05839177bf0d6e43a5840 Signed-off-by: Jihoon Bang <jbang@nvidia.com> Reviewed-on: http://git-master/r/130945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10ARM: mutex: use generic atomic_dec-based implementation for ARMv6+Will Deacon
Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+") removed the barrier-less, ARM-specific mutex implementation in favour of the generic xchg-based code. Since then, a bug was uncovered in the xchg code when running on SMP platforms, due to interactions between the locking paths and the MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place lock in contended state after fastpath_lock failure"), however, the atomic_dec-based mutex algorithm is now marginally more efficient for ARM (~0.5% improvement in hackbench scores on dual A15). This patch moves ARMv6+ platforms to the atomic_dec-based mutex code. Change-Id: I8f64e98ccb61cc1cb9cb68ee15e55d8a792792f5 Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-on: http://git-master/r/130941 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+Will Deacon
The open-coded mutex implementation for ARMv6+ cores suffers from a severe lack of barriers, so in the uncontended case we don't actually protect any accesses performed during the critical section. Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec code but optimised to remove a branch instruction, as the mutex fastpath was previously inlined. Now that this is executed out-of-line, we can reuse the atomic access code for the locking (in fact, we use the xchg code as this produces shorter critical sections). This patch uses the generic xchg based implementation for mutexes on ARMv6+, which introduces barriers to the lock/unlock operations and also has the benefit of removing a fair amount of inline assembly code. Change-Id: I58e3ca4d2740a834d30b54fc35742fa2df7792ad Cc: <stable@vger.kernel.org> : 0bce9c46: mutex: Place lock in contended... Cc: <stable@vger.kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Reported-by: Shan Kang <kangshan0910@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/130940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10tegra: colibri_t20: incorporate l4t-r16 changesMarcel Ziswiler
Incorporate L4T R16 changes from NVIDIA Ventana. Note: USB OTG port not functional as of yet.
2012-09-10Merge branch 'l4t/l4t-r16' into colibriMarcel Ziswiler
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
2012-09-10tegra: colibri_t20: USB clean-upMarcel Ziswiler
Re-enable USB Ethernet gadget. Clean-up USB platform data.
2012-09-06arm: tegra: xmm: add post_resume phy callbackVinayak Pane
phy post_resume is called when usb port+hub is resumed, check if modem has finished resume by then. Notify modem about post resume by setting bb_wake to low. Modify check for CP initiated wakeup to read current modem state (ap_wake). Bug 1034420 Change-Id: Ie9a3aa581bd7660183464e3fc2554ceb055b69b2 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/129533 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-06arm: tegra: secureos: disable L2 as part of sleep CPU SMCChris Johnson
This is an alternate way to have the L2 disabled available with later TL secureos versions. In this version, the sleep CPU SMC which is the last one issued before entering LP2 on CPU0, will also disable the L2 without a flush of the secureos workspace. Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/128951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao <jamesz@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-09-05ARM: tegra: enterprise: enable wl18xx wireless module supportRakesh Goyal
Bug 990784 Change-Id: I173df3f7244e7d0b40ae5aad98c72885ff42fdab Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: http://git-master/r/129103 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-05ARM: tegra: tai: fix gpio number for nfc and bluetoothRakesh Goyal
NFC use GPIO4 for download firmware BT_RST is required to make bluetooth on/off Bug 1002637 Change-Id: Ic49a3fe606de618dfafdf0bc35b6a6fc1ac12cdd Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: http://git-master/r/128612 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-05arm: tegra: kai: update memory timingsKerwin Wan
bug 947148 Change-Id: Icc9711e44375dee9346cbe2cb8af090286a244a2 Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/126834 (cherry picked from commit 90ec2d7e47927723f8c088c178bb560828fac622) Reviewed-on: http://git-master/r/129571 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-09-05arm: tegra: phy: enable wakeup event for usb phyRakesh Bodla
If usb device already connected, should disable WKCN in USB2D_PORTSC1, and enable WKDS in USB2D_PORTSC1, during utmi phy power off. All the wakeup resource should be cleared after the event happened. Bug 1020021 Bug 1028429 Change-Id: I807ca76d4392318adf6adb808cb2bf290cd0d60c Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/128547 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-09-05ARM: tegra: kai: adjust ov2710 power sequenceSang-Hun Lee
Update the power sequence to match the specification Bug 1031318 Reviewed-on: http://git-master/r/124496 (cherry picked from commit d2b1e1ddb2e65482eb15698b925471daf573a7ba) Change-Id: I837cafb494571816ee6ef25ea8159fc0de9fb2f5 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/128945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-03ARM: tegra: cardhu: set I2S as slave modeChandrakanth Gorantla
enable slave mode for cardhu platform. BUG 998682 Change-Id: Iad330677154af417e0848059536581bcabdd98bc Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-on: http://git-master/r/128734 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-09-03video: tegra: dc: support for vblank syncRakesh Iyer
Add wait for vsync support for one-shot panels. The code supports extension of this feature to other panels. Bug 1033411. Change-Id: Ie4d6cb45e5de81083458169ccdfa33230235ed72 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/128927 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2012-09-02tegra: colibri_t20: fix i2c usageMarcel Ziswiler
The I2C2 controller is used for display EDID via DDC_CLOCK/DATA on X3 pin 15/16. The regular GEN2_I2C pins can not be used for I2C functionality on the Colibri T20. The I2C3 controller can optionally be used via CAM/GEN3_I2C on SODIMM pin 127/133.
2012-08-31enterprise pinmux: set the pinmux for audio portsNikesh Oswal
Bug: 1039342 Reviewed-on: http://git-master/r/127868 (cherry picked from commit 92f2d2099e3411dfa1966e8ead58dc5654f3124c) Change-Id: Ibe7dd39a06170766ec043ccbf18df0078ee9e7cb Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/128508 Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-08-29i2c: tegra: rename fast clock and div clockLaxman Dewangan
Rename fast clock to "fast-clk" and div clock to "div-clk" in driver and clock table to have aligned with mainline as: This is based on change: --------- commit f16e6e77a105ec53496f0d8343895da342917873 Author: Laxman Dewangan <ldewangan@nvidia.com> i2c: tegra: pass proper name for getting clock --------- Change-Id: Ie9a1972a18e2e60ac7c84c4509860cf72405ef16 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128150
2012-08-29arm: tegra: tai: keep smps4 ONSeema Khowala
Bug 1029431 Change-Id: I79ba7e363feeaec86912445ce005ea65a3960718 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127994 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29ARM: tegra: tai: Add tai machine numSeema Khowala
http://www.arm.linux.org.uk/developer/machines/list.php?id=4311 Bug 1002637 Change-Id: Id52214c1780294e4e4a6607b954c05e9be950fdd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127978 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: config: Add TaiSeema Khowala
Bug 1002637 Change-Id: I33d38ab3a5395f85564ef9a3282db152b4d79113 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/127974 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: cardhu: change parameters for emc 266.5mhzWen Yi
The EmcTclkStable is set to 0x00000004 and McEmemArbOutStandingReq is set to 0xc0000030 Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122302 (cherry picked from commit a3a1d1797e310d61204256af8be995f9396c22e7) Change-Id: Ic65334a6573582ae99d05a8f6f8290096755827e Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/127458 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: cardhu: correct EMEM_ARB_CFG in emc dfs tableWen Yi
The memory frequencies 266.5mhz and 437mhz have incorrect EMEM_ARB_CFG set in emc table of Samsung part. That resulted in emc scaling completely disabled and emc runs at 533mhz all time. The settings have been corrected to 0x00000008 and 0x0000000D. Bug 1030392 Bug 1039060 Reviewed-on: http://git-master/r/122163 (cherry picked from commit f691268c138b9ed31b3867b049e64c121ecb188e) Change-Id: I13f89c19af5391743aeba348f4a3ca4a73307bdf Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/127429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
2012-08-29arm: tegra: Enable LP1_950 configKarthik Ramakrishnan
Enable LP1 Core voltage settings to 950mV The feature is added in the below change. Refer to http://git-master/r/#change,124135 for more details. Bug 1035684 Change-Id: I922efff17797f4666fd6ed069a8523c164445842 Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit 0f5d34db547ca6bfb9c0bae0b0048f58ba71c833) Reviewed-on: http://git-master/r/124781 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: Board files settings for LP1 0.95V CoreVKarthik Ramakrishnan
Set the register values for each of the board files to keep the Core voltage to 0.95V in LP1. This change is only for those platforms where LP1 is supported. Enterprise and Kai are the main platforms for this change. There is no support for Cardhu for LP1 and so is left blank and the feature will be skipped for Cardhu platforms, except for AP37. AP37 with a PM269 board needs this change and so Cardhu board file is updated with the values specific to AP37. This change is part of the feature to set VCore to 0.95V Refer to http://git-master/r/124135 for more details Bug 1035684 Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a) Reviewed-on: http://git-master/r/124780 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-28Revert "Revert "ARM: tegra: enterprise: update memory timings""Simone Willett
This reverts commit 0405128605ed7a858aecb8fb9aaaf80e0e44c4b8 Change-Id: I3a0ee9b0079b884d53c43323e21b472a40c31bb7 Reviewed-on: http://git-master/r/125323 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
2012-08-28video: tegra: cardhu: Default bpp from hardwareChristopher Freeman
This patch adds: 1. A kernel config option that hints to DC driver to use the current value of the color depth register as the default for initializing the FB driver. 2. Checks to see if DC is enabled before reading off the color depth register in tegra_dc_probe. Change-Id: I852cc1328fcf42f33052f46b86d753e691744329 Signed-off-by: Christopher Freeman <cfreeman@nvidia.com> Reviewed-on: http://git-master/r/127297 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-28arm: tegra: p1852: set FPDLink latch clock edgeDongfang Shi
Make parallel data strobed on rising clock edge For SKU2 MODS get correct CRC. Bug 995623 Change-Id: I70f4b87e781821cf4ff8370c17b79f5bea7dc55c Signed-off-by: Dongfang Shi <dshi@nvidia.com> Reviewed-on: http://git-master/r/121824 (cherry-pick from 5200d0f10b936e00dbc2a946eed8c2e48b039943) Reviewed-on: http://git-master/r/122537 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-08-28E1853 BRINGUP Linux Snor: Micron SupportBob Johnston
Expanding NOR functionality to work with ADMUX and Burst mode for Micron Support in E1853. Bug 989919 Bug 966833 - Adding fields for picking MUX vs NONMUX and picking Async, Paging, Burst mode for reads - Added run time decision between them - 1853 specific settings for Async NOR - 1852 specific settings for NOR - 1853 NOR timings changed Reviewed-on: http://git-master/r/122286 (cherry picked from commit a242e7194c7de559d22fe5b275a8782086f10e50) Change-Id: I79de1d52d4c7199c83b380c2fa6d8cae6b35f09d Signed-off-by: Bob Johnston <BJohnston@nvidia.com> Reviewed-on: http://git-master/r/124946 Tested-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-08-28ARM: tegra: enable errata 727915 for Tegra3Kirill Artamonov
By-way maintenance doesn't reliably work with enabled lp2_in_idle on Tegra3 platform which uses R3P1_50 revision of pl310. Enable errata 727915 for Tegra3 to avoid system hang. Change-Id: Ia296c1d5b35b8f28353c15d1e4622686bc7d3beb Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/127225 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-02 05:15:39 +0000