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It appears that the default code copied from Freescale routes parallel CSI
to IPU1, which is the IPU that we are using for MIPI-CSI. Change the route
from parallel to MIPI
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(cherry picked from commit f77f22601e4f4bcbf3e14a48266a4fe3fa56e6e0)
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Fix error included when checkpatch errors were fixed
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Running scripts/checkpatch.pl -f on baseboard-wand.c results in many
formatting errors that are not critical but would cause some problems
if we were to upstream this code.
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Fix a small bug when excluding MIPI from the build configuration. There
was a '2' missing at the end of the CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2
var.
Also, reorganized the code so that all of the IPU capture, MIPI, and sensor
init is called using wand_init_mipi_csi(), which is a stub now when MIPI
is deslected.
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(cherry picked from commit 11a509c6d0958741af52fd85661c08975d1e271d)
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(cherry picked from commit 1c1fd4c1721b3c778a583c41daaf6eaef86fc2f4)
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(cherry picked from commit 65bdd402ba6967518794f3379339fb0a469a976c)
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(cherry picked from commit 26c6d7b49f9d59d43ec166a97eb2cb8d519d1441)
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Commits 13c1310c and 7361e1f0 attempt to read undocumented memory
bits (as of TRM released 2013-05-30) to determine CPU speed rating.
This calculation appears to disable 1GHz mode for (some?) iMX6 Solo
and DualLite CPUs sold by Freescale as 1GHz parts.
This patch reverts the changes and hard-hacks the maximum speed to
1GHz for all iMX6 parts until more information is available.
(cherry picked from commit 177c82740df1a817ccbe978ca687246e77a0718b)
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The IOMUXC_GPR13 control register has different functionality on iMX6S/iMX6DL
(cherry picked from commit 2a118bb2c07da80ad8906387d75c0b083ec9e619)
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In the event that a I2C bus is disturbed, for instance by a slave missing
a clock pulse, it is desirable to have a way to get the bus back working
other than by power-cycling the whole system. This patch makes it possible to
to have a special function in board support code issue an I2C reset, since
the IMX peripheral is not capable of doing this, and it needs to be done
by bit-banging the corresponding pins in GPIO mode.
The reset function needs to check if the bus is hung by checking the state
of SDA and issue a reset by pulsing SCL a few times as long as SDA is low.
Signed-off-by: David Jander <david@xxxxxxxxxxx>
Conflicts:
drivers/i2c/busses/i2c-imx.c
(cherry picked from commit c1c409c8e9f96e1bd16717733c7456497b42d558)
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without CPU_FREQ
Conflicts:
arch/arm/plat-mxc/dvfs_core.c
(cherry picked from commit 1195fac5d0324c267660b706f5e347e003728d13)
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(cherry picked from commit 59d6b4294f5f43c75a9cf4b3cc12bca9bf122e24)
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Update the wandboard defconfig file to reflect a closer alignment to
the default configurations of the Freescale reference boards. Here
is a high-level summary of changes:
- Disable SWAP, as we do not have a swap partition
- Enable/disable certain ARM errata workarounds
- Enable audio and SGTL5000
- Build all cpufreq modes
- Touchscreen and keyboard input support
- DRM support converted from built-in to modules
- Added some USB gadget support
- Added default crypto options and hardware crypto support (FSL CAAM)
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Adds MIPI-CSI support for Wandboard
Upstream-Status: Inappropriate
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clk structure member name is defined only when CONFIG_CLK_DEBUG is enabled.
Hence need to encapsulate the code with this config.
Patch received from imx community:
https://community.freescale.com/thread/308482
Signed-off-by: xiongweihuang
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value. However the memset itself became broken
by that patch for misaligned pointers.
This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.
Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.
While at it, the entry instructions are slightly reworked to help dual
issue pipelines.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 418df63adac56841ef6b0f1fcf435bc64d4ed177)
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optimizations
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 455bd4c430b0c0a361f38e8658a0d6cb469942b5)
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Add missing parenthesis
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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There is single method to set clock-rate for both audio and video pll-s
in i.MX6q clock system implementation. That's possible due to they have
similar set of registers with a different bases. But there is also one
common register: CCM_ANALOG_MISC2, which contains post-dividers.
In current implementation, independently of whether audio or video clock
is going to be set, the mask 0xc0000000 is applied to MISC2 register.
This means, that if the audio clock rate is changed, the video clock
post-dividers possibly will be corrupted.
This patch fixes the issue described above.
Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
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Correct the definitions of ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK and
ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK to 0x03000000 and 0x30000000 respectively
Signed-off-by: Peter Chan <B18700@freescale.com>
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sdma: bd is bufferable dma buffer, interrupt handler can not get correct
data after sdma script updated. Which will cause there is no interrupt
after failed period number times in the interrupt handler.
This is a workaround.
Signed-off-by: b02247 <b02247@freescale.com>
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imx6dq have 3 i2c controllers and 5 ecspi,imx6dl have 4 i2c4
controllers and 4 ecspi. imx6dl i2c4 clock source is routed
from pll3 through to ecspi_root gate.
Add i2c4 bus support for sabresd/auto, and arm2 platforms.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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In order to fix the performance issue on ENET when WAIT mode
is activated, route the ENET interrupts to a GPIO on all MX6DL boards.
This patch must be applied on top of:
MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active
808863866d2c17aeb3e70a7fcd094bd96db4b601
bae4d40849f3acdd9663f5a0857c9415ed7e6d5d
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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For MLB uses iram for data transfer, and there's a missing of dependency
on iram in MLB's clock setting, MLB can't receive data in wait mode.
We need to add ocram clock dependency in MLB clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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This reverts commit 067c8dcfa79a169d86809272569fe734c4222c79.
i.mx6dl/dq sabreauto/sabresd board will boot up failed
randomly with this patch-set, thus revert it. [Jason]
Signed-off-by: Jason Liu <r64343@freescale.com>
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* Correct mipi-csi2 settings only one data line is used
* Add mx6q_mipi_csi1_io_init ipu-csi setting callback
use virtual channel 1 and attach it to CSI1 -> IPU0
* Set i2c slave address to 0x52
* Set ipu-csi clko_clk
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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After enable PICE in kernel config, building will meet
fatal error:linux/wakelock.h: No such file or directory
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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Set the proper pad values for the pins used for address.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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These timings are calculated from the M29W256GL7AN6E.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This reverts commit 58209e14383520d58b1bf74e0e9f98f7d05b80c6.
After apply these two patches, we can not pass the stress test.
So revert these two patches.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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All of the interrupts from the ENET block are not routed to
the GPC block. Hence ENET interrupts are not able to wake
up the SOC when the system is in WAIT mode. And the ENET
interrupt gets serviced only when another interrupt causes
the SOC to exit WAIT mode. This impacts the ENET performance.
To fix the issue two options:
1. Route the ENET interrupt to a GPIO. Need to enable the
CONFIG_MX6_ENET_IRQ_TO_GPIO in the config.
This patch provides support for routing the ENET interrupt
to GPIO_1_6. Routing to this GPIO requires no HW board mods.
If the GPIO_1_6 is being used for some other peripheral,
this patch can be followed to route the ENET interrupt to
any other GPIO though a HW mode maybe required.
2. If the GPIO mechanism cannot be used and is not enabled
by the above mentioned config, the patch will disable entry
to WAIT mode until ENET clock is active. When the ENET clock
is disabled, WAIT mode will be automatically enetered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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If not, the clocks usage will be mismatch
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Add NULL pointer check for global fsl_xcvr_ops
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Sabre ARD include WEIM-NOR configuration update to
enable higher bandwidth on this interface for mfg tool
support (imx6_updater_defconfig).
Signed-off-by: Alex Sierra <b18039@freescale.com>
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Set proper pad value for WEIM NOR. Without setting these pad value
the weim-nor can not work.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The previous patch ENGR00251630 didn't notice mx6q_revision() will
return -EINVAL and will match 'mx6q_revision()<IMX_CHIP_REVISION_1_1'
,then mx6dl TO1.1 will also change suspend state to 'standby'.
Signed-off-by: Robin Gong <b38343@freescale.com>
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For MX6DL,align max cpufreq judge by SPEED_GRADING fuse bit with MX6DQ.
For MX6SL without the fuse bit, we need add condition check, if found
arm_max_freq set by default , change to1G. Else decided by 'arm_freq'
setting by cmdline.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Support LVDS1 and HDMI dual display on SabreSD Rev.C board on i.mx6
By default, LVDS uses LDB_SEP1 mode due to the hardware design.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Config clock,irq,mux pad,data entry, etc to setup uart5.
Signed-off-by: Jianzheng Zhou <jianzheng.zhou@freescale.com>
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- enable the auto detect for parallel ov5642 and ov5640 in sabresd board.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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- enable the auto detect for parallel ov5642 and ov5640 in sabrelite board.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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The vfp_enable function enables access to the VFP co-processor register
space (cp10 and cp11) on the current CPU and must be called with
preemption disabled. Unfortunately, the vfp_init late initcall does not
disable preemption and can lead to an oops during boot if thread
migration occurs at the wrong time and we end up attempting to access
the FPSID on a CPU with VFP access disabled.
This patch fixes the initcall to call vfp_enable from a non-preemptible
context on each CPU and adds a BUG_ON(preemptible) to ensure that any
similar problems are easily spotted in the future.
Cc: stable@vger.kernel.org
Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com>
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[Fix merge conflict]
Signed-off-by: Jason Liu <r64343@freescale.com>
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There is a bug when we try to remove wakeup module twice as
g_ctrl is a globle variable, in fact, it is per controller
wakeup driver, so the private data should be per device.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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