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Sdma iapi start loading sdma script by write HSTART register as
memory. When instruction reorder and IRQ delay may let the next
synchronize operation wait forever.
We change it by using writel() to access sdma registers,
and introduce timeout to show this error.
HSTART and STOP_STAT contain bits that are reset by hardware.
So if we read-modify-write, we are in danger of setting a bit
after SDMA has cleared it.
The spec calls these registers "write-ones" register. So the
ARM can write a 1 to any bit, but does not need to worry about
clearing any bits that were previously set. SDMA hardware
keeps track of all bits that were set.
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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If enabling DVFS core and enter suspend state, FEC resume was
failed due to wrong clock. This is because enter_lpapm_mode_mx51
function doesn't set low_bus_freq_mode flag after commit 30f6fc381.
It causes the system is in wrong low bus mode.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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MX53 loco&smd:preset suspend voltage in the latest stage because
Da9053 use the same register for preset and normal mode
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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CPU working point needs to be initialized based on the current CPU
frequency in start_dvfs() and should correspond with the correct entry
in the cpu_wp_auto table.
If its not initialized correctly, DVFS-CORE will fail when PLL-relock
results in a frequency that is not the same as set in the cpu_wp_auto table.
So fix it by finding the entry that closely matches the CPU frequency.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Restructure MX53 bus frequecy driver,
Add handlers for DDR3 boards,
MX53 DDR2 handlers not implemented in this patch
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Only preset voltage for suspend to mem mode
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Use arm_podf to switch cpu frequency when the pll_rate is
same. Remove pll settings for 400MHZ, 160MHZ since they
use arm_podf for cpu frequency change. For 1.2GHZ, 1GHZ,
800MHZ working point, relock pll is used. So pll settings
are kept.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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add 100ms delay after BT chip reset, make it work stable.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Current set_low_bus_freq codes enter low bus frequency automatically
if the CPU frequency is the lowest one. If only have one working
point, it enters low bus state in boot up phase. It causes mx53 RevA
board hang up in boot phase. And it also causes the bus frequency of
mx53 ard is reduced.
This patch doesn't allow to enter low bus state if only have 1 WP
Signed-off-by: Lily Zhang <r58066@freescale.com>
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add defconfig, remove gpio power key
fix some defconfig item miss
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Add max11801 touch screen driver for MX53_ARD.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Make sure only DA9053 irq configured as wakeup source for mx53 smd &loco
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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This patch adds TVDAC regulator for TVE platform data.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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enable performance monitor driver for system loading analysis
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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enable performance monitor driver for system loading analysis
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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1) Enable WiFi power during system boot up or WiFi card can not
be detected.
2) Remove BT Power on/off control in RFKILL function because bt/wifi
are sharing one regulator and has conflicts on power control.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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Change key order per MX53 SMD board design.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This patch adds Seiko WVGA LCD panel support.
Note that you need to populate D4 on the LCD board.
You need to use this fb videomode:
video=mxcdi0fb:RGB24,SEIKO-WVGA
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch changes to use OV3640 defaultly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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add cea ext block parser.
it provide more video modes and the info of device HDMI compatible.
Signed-off-by: Jason Chen <b02280@freescale.com>
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The parent clk of asrc serial clk is PLL4. After PLL4 clk is
changed as 455MHZ in U-Boot, asrc serial clk is not right.
So the patch uses round_rate to set asrc serial clk and make
it pass clk rate check.
This patch also moves asrc serial clk set from board file to
clock file.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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mx50rdp, mx51bbg, mx53evk:
Add get keypad press status callback and desired send key value
to the platform data.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add mx53 smd&loco suspend via i2c command
Only a maximu 30ms delay before da9053 enter suspend, thus
the command is sent out at the latest stage of system suspend
operation when all other drivers already suspended and irq disabled.
A standalone polling-mode i2c interface is therefor deployed for the suspend
command operations.
In current solution, mx53 fails to resume from 1GHZ working poing when reduce
VDD &VCC to stop mode level. Thus a workaround is added to set mx53 working
point to 400MHZ before suspend and restore to previous working point after
it resume back.
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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- Since Hardware DVFS core is used, CCM.CDCR.[software_dvfs_en]
needs to be set as 0. This patch is the supplementary patch of
commit f59dc9fcc5. It handles the case for PLL switch of 1GHZ
- In HFS mode, all the shadow registers are used. So add the codes
to support HFS mode when changing PLL.
- For DVFS core, when switching PLL, ARM_PODF also needs to be
considered.
- DVFS core parameters need to be tuned further.
- DVFS core and CPU frequency have conflict and can not be used
together now.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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- Set working points for different part numbers according
to RevD datasheet.
- Put MX53 working point settings in new files.
- For Auto, only 800MHZ working point is added. Since the SW uses
PLL1 to judge chip part number now, the chip will be treated as
auto chip if the user set PLL1 as 800MHZ in U-Boot. If there is a
better way to get part number information, we will revise part
number setting codes in clock.c.
- The voltages for 160MHZ is "TBD" in datasheet. Set it as
0.9V firstly.
- To run 1.2GHZ CPU, do as the following in U-Boot:
i2c mw 0x48 0x2e 0x60
clk core 1200
Before executing the command, you must ensure your chip is
1.2GHZ chip
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Fix many IOMUX pad settings so that the suspend power is improved.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Added APIs to read single and multiple IOMUX pad settings.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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MX53_TO2: DVFS core caused system hang.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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Clear SYS_ON_OFF_CTRL(GPIO7) as 0 to power down
the system.
SW19 must be put as location 2 to make it take
effect.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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- Add LOCO GPIO keys, add power key to SMD board.
- Enable GPIO key in default config.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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- Add MX53 SMD and LOCO board support
- Build in SATA, DA9053 regulator
- Remove unnecessory drivers
Signed-off-by: Lily Zhang <r58066@freescale.com>
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To fix the compile error for device only function for OTG port.
Add macro to differetiate the host and device function.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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To fix the compile error for device only function for OTG port.
Add macro to differetiate the host and device function
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Build the SATA AHCI driver in kernel Image.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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By defining the regulator name in the esdhc platform data,
the esdhc driver will dynamically check and set a proper voltage
for the card.
This can fix the issue that SD32 can not work well on mx50 rdp board
because the default voltage of VSD seems can not meet its requirement.
This is only a workaround.
The root cause may be related to HW, board degsin or WiFi card.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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Move mx5x usb wakeup interrupt handler from the driver to MSL
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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There were two places to handle wakeup irq routine, one is MSL,
The other is at driver. It increases the complexity for maintaining
and reading. So, in this serial of patches, I move the wakeup irq
handler from the driver to MSL. The main changes like belows:
For wakeup event, classify the wakeup event like below:
enum usb_wakeup_event {
WAKEUP_EVENT_INVALID,
WAKEUP_EVENT_VBUS,
WAKEUP_EVENT_ID,
WAKEUP_EVENT_DPDM,
};
For host driver, it is better to delete ehci_fsl_pre_irq,
and put related wakeup operation to usb_wakeup thread at MSL code.
As at MSL, It can't touch usb hcd struct, I have exported one function
at fsl host driver to handle hcd issues.
For device driver, move wake_up_irq to usb_wakeup thread at MSL code
Revert the commit that changing mutex_lock to spin_lock_irqsave at udc_resume.
The reason is the clock related function should not be called at irq_disabled
situations and interrupt context.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Some error return values are meanless, change them to
meanful values.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Enable MMA8450 accelerator support for i.mx50 evk.
Signed-off-by: Sammy He <r62914@freescale.com>
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The old code only debounce vbus and id value for OTG mode,
these value should be debounce for all usb mode,
including usb device only mode, usb host only mode, and usb otg mode.
Besides, It also changes the debounce function name from
usb_debounce_id_pin to usb_debounce_id_vbus, it will be more
clear for reader.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For mx1_defconfig this yields:
add/remove: 1/0 grow/shrink: 1/4 up/down: 49/-108 (-59)
function old new delta
imx1_imx_uart_data - 48 +48
kernel_config_data 7277 7278 +1
imx_add_imx_uart_1irq 132 128 -4
imx_add_imx_uart_3irq 164 156 -8
scb9328_init 96 64 -32
mx1ads_init 220 156 -64
for mx21_defconfig this yields:
add/remove: 1/0 grow/shrink: 0/3 up/down: 64/-52 (12)
function old new delta
imx21_imx_uart_data - 64 +64
imx_add_imx_uart_3irq 160 156 -4
imx_add_imx_uart_1irq 140 136 -4
mx21ads_board_init 220 176 -44
for a random mx25 config this yields:
add/remove: 1/0 grow/shrink: 0/5 up/down: 80/-56 (24)
function old new delta
imx25_imx_uart_data - 80 +80
imx_add_imx_uart_3irq 160 156 -4
imx_add_imx_uart_1irq 140 136 -4
mx25pdk_init 288 272 -16
eukrea_mbimxsd_baseboard_init 272 256 -16
eukrea_cpuimx25_init 252 236 -16
for mx27_defconfig this yields:
add/remove: 1/0 grow/shrink: 0/10 up/down: 96/-280 (-184)
function old new delta
imx27_imx_uart_data - 96 +96
imx_add_imx_uart_3irq 160 156 -4
imx_add_imx_uart_1irq 140 136 -4
pca100_init 560 544 -16
mx27pdk_init 112 96 -16
mx27lite_init 92 76 -16
eukrea_cpuimx27_init 332 316 -16
pcm038_init 388 348 -40
mxt_td60_board_init 320 280 -40
eukrea_mbimx27_baseboard_init 476 436 -40
mx27ads_board_init 368 280 -88
and finally for mx3_defconfig:
add/remove: 2/0 grow/shrink: 0/9 up/down: 128/-344 (-216)
function old new delta
imx31_imx_uart_data - 80 +80
imx35_imx_uart_data - 48 +48
imx_add_imx_uart_1irq 132 128 -4
imx_add_imx_uart_3irq 164 152 -12
mx31moboard_devboard_init 360 344 -16
mx31lite_db_init 176 160 -16
mx31moboard_smartbot_init 384 360 -24
kzm_board_init 232 208 -24
armadillo5x0_init 392 364 -28
mx31lilly_db_init 248 208 -40
mxc_board_init 3760 3580 -180
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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This patch adds OV5640 and OV5642 camera driver support in
imx5_defconfig. They will be built as modules.
Signed-off-by: Liu Ying <b17645@freescale.com>
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1) Add platform data for OV5640 camera.
2) Add camera reset and power down support.
3) Use ssi_ext1 clock as mclk for camera.
Signed-off-by: Liu Ying <b17645@freescale.com>
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Fix a typo which miss by patch apply.
It will cause make defconfig give a warrning.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add hdmi support for SMD/LOCO platform.
Signed-off-by: Jason Chen <b02280@freescale.com>
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enable ATH3K and mx53 SMD Bluetooth RF kill configs.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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There is a clock issue when UART3 enable DMA, so disable this.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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MX53 SMD board use ath3k Bluetooth Chip.
Add rfkill interface to control AR3K BT's power and reset.
when power on bt, it require to reset BT chip.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Enable SRTC driver in MX5 defconfig.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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