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2011-09-16ENGR00156850 gpu-viv: add gpu-viv driver sourcerel_imx_2.6.38_11.09.01Richard Zhao
It's vivante driver 4.5.0 (Sep 5, 2011) with freescale changes. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Lily Zhang
2011-09-16ARM: twd: register clockevents device before enabling PPIWill Deacon
The smp_twd clockevents driver currently enables the local timer PPI before the clockevents device is registered. This can lead to a kernel panic if a spurious timer interrupt is generated before registration has completed since the kernel will treat it as an IPI timer. This patch moves the clockevents device registration before the IRQ unmasking so that we can always handle timer interrupts once they can occur. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-09-16ENGR00156849 MX6Q: add relative clock for BCHHuang Shijie
The BCH needs the pl301_mx6qperl_bch clock. The BCH will not work if the clock is not enabled. So add it. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-09-08ENGR00155147 mx5x mx6x: adjust dma zone max size to 184MJason Chen
adjust dma zone max size to 184M. keep default size as 96M. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00155135-2 ipuv3 dev: add processing driver supportJason Chen
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing support, this patch make all these features into one processing driver. A struct ipu_task is the interface between user and this driver, user just need fill his task struct and queue it through ioctl, then wait ipu hardware finish its job (now only support BLOCKING operation, not support NO_BLOCK operation). Pls refer to inlcude/linux/ipu.h for structure information and unit test for usage. This patch is for MSL file change. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-08ENGR00156232 [mx6q]change cpuinfo keywordTony Lin
MX[0-9] is the keyword for multimedia applications, so change the cpuinfo from i.MX 6Quad to MX6 Quad Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-06ENGR00156153: MX6- Fix bugs in clock code.Ranjani Vaidyanathan
Refer to the ipcg table in the spec to ensure that the parent clocks are set correctly. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-02ENGR00155981: MX6: Fix crash caused by cpufreq during suspend/resumeRanjani Vaidyanathan
Random crashes occur in CPUFREQ code when resuming from suspend. The root cause is due to freeing and allocating of common data structure (frequency table) shared among all the CPUs. Fix the code by ensuring that the common data structure is only created and deleted once. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-02ENGR00154436-1 - MACH-MX6: MXC HDMI updates to support full feature setDanny Nold
- Corrected logic bug in how GPR registers are set - Add support for configurable ipu-to-hdmi mappings - Add aspect ratio to EDID mode data - Expanded HDMI register field defines - Removed HDMI platform data now handled by HDMI core in MFD Signed-off-by: Danny Nold <dannynold@freescale.com>
2011-09-02ENGR00155958: MX6: Fix bug in setting parent of periph_clkRanjani Vaidyanathan
periph_clk mux should be set only after the periph_clk2 mux is set. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-02ENGR00155912 [mx6q]clock: correct pll disable functionTony Lin
pll3 and pll7 have opposite power down bit definition comparing with other plls. so reverse the bit when setting these two plls Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-02ENGR00155893 [mx6q]clock: correct set parent functionTony Lin
set periph_clk_sel to derive clock from periph_clk2_clk Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-02ENGR00155890 [mx6q] code clean upTony Lin
remove unnecessary '\' Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155845-2 mfd for hdmiAlan Tull
This is a mfd for the internal HDMI Transmitter on i.Mx. It handles resources that are shared by the seperate video and audio drivers. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-09-01ENGR00155715: MX6: Fix warnings is clock and cpufreq code.Ranjani Vaidyanathan
Fixed warnings in clocks and cpufreq code. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-09-01ENGR00155759 [MX6]MMDC clock should be always onAnson Huang
1. We should enable mmdc_ch0 clock in init to make its usecount > 0, or ipu's parent is mmdc_ch0, when ipu enable/disable clock, mmdc_ch0 will be also enable/disable, cause system hang when disable. 2. Remove build warning of unuse variable. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155731 [MX6]clock disable should functionAnson Huang
un-comment __clk_disable function and __clk_disable_inwait function. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-09-01ENGR00155612-1 [mx6q]dynamically sd pad setting changeTony Lin
on mx6q, it supports sd3.0 card with DDR 50MHz, SDR 100Mhz and SDR 200MHz. sd pads have to be changed dynamically for these large scale of clock frequencies. add different pad setting definitions for these clock frequencies under board file, since these settings are really board dependent. add callback funtion in sdhc platform data to give driver approach to change pad setting according to current clock frequency. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-09-01ENGR00155718 [MX6]CPUs hotplug sometimes failAnson Huang
Sometimes when system very busy,hotplug may fail because CPU0 has no chance to kill secondary CPUs from hardware,secondary CPUs keep enter/exit wfi ,and we have a printk after wfi,that makes CPU0 has no chance to kill secondary CPUs,we should remove this printk. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-30ENGR00139280: MX6: Add CPUFREQ supportRanjani Vaidyanathan
Add support for CPUFREQ for SMP system. Added support for 1GHz, 800MHz, 400MHz and 160MHz. Added support for scaling the voltage along with frequency. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-08-30ENGR00153925 MX6Q: Fix EGA touch failure on lvds2 portFrank Li
lvds2 port use i2c3 port. Add EGA i2c register data to i2c port3. but two touch can't work at the same time because irq conflict. Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-08-29ENGR00139255-1 MX6Q_BSP ESAI: Add esai recording supportLionel Xu
Add ESAI recording to mx6q platform. Note: since there is pad conflict between esai record and fec, add a boot argument esai_record to deal with it. This argument is required to enable the record functionality. Signed-off-by: Lionel Xu <R63889@freescale.com>
2011-08-29ENGR00155151 imx6q clock: fix ldb and ipu-di clock enable registerJason Chen
ipu2-di should use CCGR3 4&5, ldb_di should use 6&7. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-08-29ENGR00155464 mx6q: Change default DMA size to 184MSammy He
Change default DMA size to 184M for mx6q. Current 96M size isn't enough for 1080P encoder + decoder, and HDMI output. Signed-off-by: Sammy He <r62914@freescale.com>
2011-08-26ENGR00155401 [MX6]Fix ipu ccm_ccgr index errorAnson Huang
ldb_di0 and ldb_di1's gating index is wrong. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-26ENGR00155391-1 [MX6]Clean up build warningAnson Huang
Fix build warning. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-25ENGR00155355 imx6: clk: add gpu axi clock to secondary of gpu core clockRichard Zhao
driver should only care about core clocks and shader clock. Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
2011-08-23ENGR00155219 [MX6]Add protection for dormant modeAnson Huang
1. clean up ddr io code, using macro define; 2. we should consider if the wake up irq comes during execution of low-power(ms6q_suspend.S) code but before ARM enter wfi, in this scenario, system will not enter STOP mode, thus, the resume code will cause system fail, so we need to consider if system can not enter STOP mode, should resume immediately after wfi. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-23ENGR00139260-3 [mx6q]add wifi driver to default configTony Lin
add wifi driver to default config as a module Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-08-22ENGR00155179-1: Change imx_viim to mxs_viimTerry Lv
This is the change for platform files. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-08-18ENGR00154748: MX5x: Add CPUFREQ and DVFS support to 2.6.38Ranjani Vaidyanathan
Enable CPUFREQ on 2.6.38 Remove the dependency between CPUFREQ and bus_freq driver. Allow for CPUFREQ and DVFS-CORE to co-exist. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-08-18ENGR00154650-1 [MX53_ARD] ESAI: add ESAI deviceGary Zhang
add EASI ARCH codes. Signed-off-by: Gary Zhang <b13634@freescale.com>
2011-08-18ENGR00154983 [MX6]Enet clock enable wrongAnson Huang
ENET should be CCM_CCGR1, CG5. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-17ENGR00154961 [MX6]system hang in suspend with irqAnson Huang
If the wakeup source irq pending during suspend process, system will hang, we need to abort suspend, and resume immediately to make system running normally. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-17ENGR00153887 mx53 ard: add display supportLily Zhang
- Add VGA support. The command option to use VGA as primary display: video=mxcfb0:dev=vga,VGA-XGA,if=GBR24 ard-vga For VGA, Need to disable Ethernet and short PIN 1-2 of J14 and J16. - Add LVDS support. The default display is LVDS0. LVDS1 needs further modification on ldb driver Signed-off-by: Lily Zhang <r58066@freescale.com>
2011-08-17ENGR00154931 [MX6]L2 cache init wrong after resumeAnson Huang
1.Need to add condition check after resum, or if we didn't config L2 cache, build will fail. 2.Need to call the mxc_init_l2x0 instead of l2x0_init. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-17ENGR00154922 [MX6]Disable some clocks during bootAnson Huang
To save power, we should disable as much as possible when kernel boot up, only leaving the necessary clocks on, devices should enable their clock in init.This is necessary for our MX6q, or the chip will be too hot, may damage. After doing this change, we can save more than 150mA@5V. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-17ENGR00154917 [MX6]Enable MMDC low-power modeAnson Huang
1. Set MMDC pad ctrl to low-power mode when dormant; 2. DRAM_RESET can't be changed due to hardware design; 3. GPR_CTLDS should be changed to lower the MMDC IO power to 0mA, but it needs hardware change, will add it in next hardware version after we figure out how to change the hardware. Current MMDC data in dormant is: IO: 28mA@1.5V; DDR: 35mA@1.5V. 4. Change the suspend code to run in iRAM; Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-16ENGR00154889-1: Add virtual iim driver to imx5 and imx6 platformTerry Lv
This patch adds platform changes to system files, including: 1. Add viim platform deivce. 2. Add viim menu. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-08-16ENGR00154890 [MX6Q]suspend/resume restore GPIO interrupt enable statusTony Lin
re-init GPIO interrupt to make GPIO interrupt workable after suspend/resume (dormant mode) Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-08-11ENGR00139261-1 [esdhc]add 8 bit mode support para in platform dataTony Lin
set to 1 if the port on board supports 8 bit MMC card. else set to 0 Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-08-11ENGR00154705 [MX6Q]suspend/resume sometimes hangAnson Huang
1. Better to write disable and reset together into SRC_SCR register; 2. Should wait for reset done. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-10ENGR00154648 [Mx6]SMP hotplug sometimes hangAnson Huang
1. boot_secondary ioremap need unmap, or the stress test of hot-plug and suspend/resume will cause the virtual address space leak; 2. Disable secondary CPUs need done by CPU0, move the SRC_SCR setting to platform_cpu_kill. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-08-10ENGR00154647 mxc: viv-gpu: squash gpu devicesRichard Zhao
gpu multi-core dirver 4.4.2 needs one single gpu device. Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
2011-08-09ENGR00154526 MX5x, SSI: audio capture not supportedZeng Zhaoming
Audio capture not support in 2.6.38 kernel, it is caused by not setting ssi correctly in clock and sync method. Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
2011-08-09ENGR00139247-5 ARM: add APBH-DMA device for imx6QHuang Shijie
add the dma device for imx6q. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-08-09ENGR00139247-4 ARM: add APBH-DMA arch code for imx6qHuang Shijie
add the arch code for APBH-DMA. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-08-09ENGR00139247-2 MX6Q: add GPMI deviceHuang Shijie
add gpmi device for sabreauto platform. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-08-09ENGR00139247-1 MX6Q: add arch support for GPMIHuang Shijie
add the arch code for GPMI. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-08-05ENGR00154108-2 imx6q MSL: make ldb support two ipu in separate modeJason Chen
make ldb support two ipu in separate mode. Signed-off-by: Jason Chen <b02280@freescale.com>
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