summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2012-07-23ARM: Tegra3: clocks: Configurable cbus dividerMohit Kataria
Added config option to set cbus divider. Bug 978870 Change-Id: I49c57064ce695dd703ad97a50b8c0d373f5a05d0 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/114197 (cherry picked from commit 3f2b0e2b973a106d62e1f4bfb75bb40bd1a96b9b) Reviewed-on: http://git-master/r/109962 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: tegra: clock: Reduce Tegra3 pll post-lock delayAlex Frid
Reduced pll post-lock delay from 50us to 2us. Rearranged wait for lock loop to delay first check of lock bit by 2us after pll is enabled. Added read fence for PLLM lock via PMC (in this case enable bit is in APB bus register, but lock detect bit is in PPSB bus register). Bug 1017271 Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115933 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: tegra: power: Enforce CPU rate range in secondary bootAlex Frid
On Tegra3 make sure cpu rate is within G-mode range before LP to G mode switch triggered by secondary cpu boot directly from LP mode. Bug 988544 Change-Id: I0d86fbf0727a6bbf6069159e7c532947a9d0af73 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115930 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Greg Lo <glo@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-20ARM: tegra: clock: relax memory efficiency if 3d clock is offPeter Zu
Bug 1003509 Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206 Signed-off-by: Peter Zu <pzu@nvidia.com> (cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30) Reviewed-on: http://git-master/r/115468 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-20ARM: tegra: dvfs: add back 916mV & 1007mV entriesPeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/113751 (cherry picked from commit 833f9d47a350358000e9201f77a3c9fd655d2900) Change-Id: I679093d9d2577625bff3e02e25ffe90d396ea5a6 Reviewed-on: http://git-master/r/116134 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-20ARM: tegra: dvfs: update Tegra3 single-core dvfs tablePeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/110587 (cherry picked from commit c0e7904245168cafc426219948ab132a4d832376) Change-Id: I370f4af1d4ce888ebc71351519c1018b82d91913 Reviewed-on: http://git-master/r/116132 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-20arm: tegra: pci: unmap/map memory while pwroff/onJay Agarwal
Rearranged the code to release all memory and res- ources whenever poweroff is called and re-allocate them whenever power on is called. Bug 963969 Change-Id: I31d9cd1e8603e638714bba765aadfdd4eed78d93 Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/116048 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-20ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-19arm: tegra3: usb_phy: HSIC rail consumes 4mA in suspendsrinivas
In auto-suspend, removed power downs for HSIC from PADS_CFG1 register. Bug 1011912 Change-Id: I646c196ef9b822ae8d9e12a0f918507fcdd16f0b Signed-off-by: srinivas <sthaduvai@nvidia.com> Reviewed-on: http://git-master/r/116044 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-19ARM: tegra: tegra2 wakeups header cleanupBitan Biswas
Removed the unnecessary function prototypes in Tegra2 wakeups header Change-Id: Ia41ce72947902cbc483cc85eaefb3a81d091a9b8 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/111817 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-19arm: config: tegra3: enable alsa usb audioRavindra Lokhande
Change-Id: I6b6348ec3b604bbf9b8e40fe551023cf94b0b153 Reviewed-on: http://git-master/r/117083 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-19ARM: mm: cache-l2x0: Implement outer_clean_all()Kirill Artamonov
There is already implemented full outer clean routine in arch/arm/mm/cache-l2x0.c. Make it possible to use it through outer_cache interface, like other outer maintenance functions. bug 983964 Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef Reviewed-on: http://git-master/r/116074 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Tested-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Justin Paver <jpaver@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-19arm: tegra: PLLX LP/G ports switching ON/OFFPrem Sasidharan
Enable target PLLX port(LP/G) before cluster switch and disable the previous PLLX port(LP/G) after cluster switch is finished. Seeing a power improvement of ~10mW when core operates at max. voltage and max. frequency. Bug 997358 Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com> Change-Id: I9d05245977f9f63a8f4c53b1c6797118d2d8b903 Reviewed-on: http://git-master/r/113399 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-19arm: tegra: p1852: Make TDM1 as 16 channelsNitin Pai
Made TDM1 as 16 channels so that both devices work in the same configuration. Bug 1008391 Signed-off-by: Nitin Pai <npai@nvidia.com> Reviewed-on: http://git-master/r/112090 (cherry picked from commit 4d042a0e613ba1c2d715d6ed47daddd61be14a28) Change-Id: I622b046b3b36147b82d47f612febb7ae7ba0767c Reviewed-on: http://git-master/r/116059 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-19ARM: tegra: dvfs: Handle Tegra3 alternative dvfs errorsRohan Somvanshi
Propagate error to the caller when switching between alternative cpu dvfs tables. Change dvfs table during cpu hotplug operation only after the new edp limit is set, and abort bringing cpu core on-line in case of failure in applying new (less conservative) table. When cpu core is removed change dvfs table before setting new edp limit, and ignore error (it is safe to continue with more conservative table). Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b) Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271 Reviewed-on: http://git-master/r/114779 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-19ARM: tegra: Fix build issue for no-SMPAlex Waterman
Fix issues causing the kernel build to fail with CONFIG_SMP not set. Change-Id: I8c7a49970e55354e38ce41d2d1e0dab00ba78f24 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/114317 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-19arm: tegra: usb: phy code clean upVenu Byravarasu
Code clean up of usb phy driver Change-Id: If951ed461b096be76938504d9e1073a70f59860a Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-on: http://git-master/r/115339 (cherry picked from commit 6d4046a6f2170dadaf5647f0bf47aa546dd705b0) Reviewed-on: http://git-master/r/104055 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-07-18ARM: tegra: enterprise: allow 3mv tolerance for cpu voltageLaxman Dewangan
Allow 3mv tolerance on minimum voltage side for cpu voltage. This saves power when system require 900/975mV. bug 997415 Change-Id: I273cdeda6980f5ddf50be7980bced443b386dae8 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/110524 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-17ARM: tegra: wake source interrupts enabledBitan Biswas
Tegra wake source interrupts are only enabled before suspend bug 904746 Change-Id: Ie9722199b4541f2bac77e47d0c8c7e65d5d8b54d Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115655 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-17ARM: Tegra3: clocks: optional se.cbusMohit Kataria
Made se.cbus optional so that se clock can be derived from other clocks and not just from the clocks which drive cbus. Added config option for the same. Bug 978870 Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/110827 (cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de) Reviewed-on: http://git-master/r/106397 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-17ARM: tegra: thermal: Call pm register only onceJoshua Primero
Fixed bug where pm register was being called multiple times. Change-Id: I32f7b10547275e0a9bdad1073f9842589180c0f8 Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/116203 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-07-17arm: tegra: pcie: Enable cardhu a02+ Dock detect GPIOJay Agarwal
Set E_INPUT and PUPD bit of GPIO_PU4 used for dock detect event for cardhu a02+ board versions and hence enable pcie hotplug for them. Bug 955043 Bug 1009086 Bug 1016722 Change-Id: Ibb66e5bc6fd9cf5333a81988b975b611fe9c5312 Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/115692 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Thota <kthota@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-17arm: tegra: xmm: flashed modem start with hsic_active lowVinayak Pane
Flashed modem should start with hsic_active signal as low. The hsic register is done at falling edge of ap_wake. Bug 1006183 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/112781 (cherry picked from commit 6437d1453d2a7694c2efa183cff135297f9f45e3) Change-Id: I7bf355088096788b030fd861ef257a9f635c66e7 Reviewed-on: http://git-master/r/115610 Tested-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Lin <stlin@nvidia.com>
2012-07-16ARM: tegra: clock: Add missed Tegra3 PERIPH_ON_APB attributesAlex Frid
Change-Id: I12be16dbc2614224ba852216a645d0f84c795334 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-07-16arm: tegra: cpu: changing cpu min. freq to 51MHzPrem Sasidharan
Changing the CPU min. frequency to 51MHz. This helps in bringing down the core power to 46mW. Bug 1005275 Change-Id: I61daa59866be7baf8ebb741000904422cb095e85 Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com> (cherry picked from commit afbb34d5871b69df328d5aae37f69f25a8946514) Reviewed-on: http://git-master/r/115452 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-16arm: config: tegra3 Enable XHCI driver for USB3Jay Agarwal
1. Enable USB3 for both android and L4T 2. Enable R8169 for android, already enabled for L4T Bug 956573 Change-Id: If8d7cf653a5cd2b02352ad07fee3a56c3f568d3a Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/113856 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Thota <kthota@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-16ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tablesAlex Frid
Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum clock limits based on recent characterization results. Bug 817679 Bug 841336 Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-16ARM: tegra: p1852: Dual-display support for all SKUsDongfang Shi
Ported Peter's original change 86413 to main. board-p1852-panel.c: Add support for primary and secondary LVDS displays, and secondary HDMI display. board-p1852-pinmux.c: Add configuration for HDMI and LVDS board-p1852.c: board-p1852.h: Support for determining which p1852 sku is in use hdmi.c:If no edid retrieved, but there's a hardwired mode, enable it (used to support HDMI->LVDS output on p1852 sku 2) devices.c:added secondary display data. Bug 977859 Bug 994011 Change-Id: Ide8fb6bf7dd873b1d50269fb98d7c1687e4d9073 Signed-off-by: Dongfang Shi <dshi@nvidia.com> Reviewed-on: http://git-master/r/100438 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16arm: tegra: usb_phy: fix hsic suspend issue on xmmVinayak Pane
XMM modem fails at auto-suspend on hsic. Fixing this issue by enabling PMC sleepwalk code conditionally and only at phy-on and phy-off routines. Bug 991709 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/109324 (cherry picked from commit 100f818a16ce97411a98ddb0e2c5c9e73a9e654a) Change-Id: If6f92b8b36f856fa633cb411ac20dbe6e862890c Reviewed-on: http://git-master/r/115612 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16arm: tegra: sd: enable sd dpdWen Yi
This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16Revert "arm: tegra: power: disable all sd dpd"Bitan Biswas
This reverts commit 8924926cdb77c6ab270867d4caef7a8cdacd11f2. Bug 924452 Bug 929628 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> (cherry picked from commit 142b34993404c853579864f7b7b4f320fb92a715) Change-Id: I9d49703799e32d410beba18938e94e4b641eea6f (cherry picked from commit 8de60b7a832bfbbf09e75def756379dbb2d14c3e) Reviewed-on: http://git-master/r/113387 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-16arm: tegra: usb_phy: utmip remote wakeup issueVenu Byravarasu
Do not clear sleep walk pointer for utmip port after remote wakeup is detected. This should be cleared after control is given to USB master from PMC. Bug 999208 Change-Id: I9f498521989c6421f0043dc1b4364591d4907423 Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> (cherry picked from commit e4dbecfe031cbacd4f22bbbcdf971ab11ad81ee8) Reviewed-on: http://git-master/r/112938 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16ARM: tegra: iovmm: Fix build error w/o CONFIG_IOVMMHiroshi DOYU
Update function prototype along with: commit 6cbf4c7465b7b70936cb422b509da0ad0829c306 ARM: tegra: iovmm: Allow alloc_client to take struct device Change-Id: I11d173429413ab268f6ab789d90f321e3d33de2c Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/115391 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-16ARM: tegra: iovmm: Make IOMMU/IOVMM selectable in KconfigHiroshi DOYU
This patch enables to replace iovmm*.ko family with tegra-{smmu,gart}.ko if needed in kernel config. To use IOMMU as backend engine, Enable TEGRA_IOMMU_{GART,SMMU} under IOMMU in config, and automatically disable IOVMM. IOVMM is equivalent to IOMMU_API. TEGRA_IOVMM_GART is equivalent to TEGRA_IOMMU_GART. TEGRA_IOVMM_SMMU is equivalent to TEGRA_IOMMU_SMMU. Change-Id: I73408e927eb3f21e1db4e73700aaf415f4949166 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/115011 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-16ARM: tegra: iovmm: Replace IOVMM backend with IOMMUHiroshi DOYU
Replace IOVMM backend functions with the standard IOMMU API ones. Instead of modifying the actual C-files in drivers, MACROs in iovmm.h does the all work. Change-Id: I27dc893555ca1495588852261e3ba1e3e5619764 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114460 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-13ARM: tegra: clock: Dynamically re-lock memory pllAlex Frid
So far Tegra3 EMC DFS allowed only scaling rates that can be divided down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM is always running at maximum SDRAM rate set at boot time, while PLLP rate 408MHz is fixed across all Tegra3 platforms. This commit implements dynamic re-locking of PLLM at run time. Now memory pll can lock either at boot rate or additional auxiliary rate that is selected as follows: auxiliary PLLM rate must be present in EMC DFS table, it must exactly match one of the rate steps for Tegra3 graphics bus with PLLC clock source (cbus), and must not be a proper factor of boot PLLM rate or PLLP fixed rate. When switching PLLM between boot and auxiliary rate, PLLC is used as backup memory pll, and during this time cbus is locked at auxiliary rate. In addition system bus is forced to temporarily use PLLP as a clock source (this is necessary as sbus main clock source is PLLM secondary divider PLLM_OUT1). Limitations: - only one auxiliary rate is supported, and it should be below PLLM boot rate, but above half of boot rate - dynamic re-lock is allowed only on LPDDR2 platforms - no clock other than EMC and system bus could use PLLM as a source; so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be selected, and VI clock (not covered by PLLM restricted configuration) must be moved to PLLP. Bug 1005576 Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/111438 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a) Reviewed-on: http://git-master/r/114760 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Increase boost_up_threshold for AVP clockVandana Salve
Increase the boost_up_threshold to 85 for ULP audio bug 1009849 Change-Id: I4b1b746f445f5c2804befa52ae95c69b6b467083 Signed-off-by: Vandana Salve <vsalve@nvidia.com> Reviewed-on: http://git-master/r/114620 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-07-13ARM: tegra: cardhu: add mem 437MHz table for Samsung K4P8G304EBJihoon Bang
Bug 1005576 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/112036 (cherry picked from commit 1f1e6d22e771336fb9e0b91bbabf12fa89f0c57c) Change-Id: If65aba6aaa0a400c960a2d2b1315a07fa44dcefe Reviewed-on: http://git-master/r/115054 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-13ARM: tegra: change include to proper notationRhyland Klein
In this case we want to include a file in the same directory. We should be using "" with include instead of <>. This fixes a an issue using the chromeos toolchain (4.6.3+) where fuse.h is not found while compiling usb_phy.c. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Change-Id: I0c6bdf6768cd89740ed0444b2b46289057dfad6a Reviewed-on: http://git-master/r/114608 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-07-13ARM: tegra: clock: Allow Tegra3 PLLM rate changeAlex Frid
Allowed Tegra3 memory PLLM rate change, provided it is disabled. Since PLLM can deviate from boot configuration now, and on Tegra3 it is controlled by PMC override registers (not CAR module registers): - Re-factored PLLM initialization, resume, and set rate operations accordingly (enable and disable ops already used PMC override). - Made sure that boot configuration is restored on entry to LP0 to match memory timing saved in scratch registers. Bug 1005576 Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110937 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8) Reviewed-on: http://git-master/r/114759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record EMC clock source rateAlex Frid
On Tegra3 added source rate to EMC clock source selection structure, and re-factored EMC DVFS initialization accordingly. Bug 1005576 Change-Id: I155e982bef2431a76cf5e5085070d4e654a7b49b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110935 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bf52c26c532a9ebabc4fc8a1fb5fc9d88be85e66) Reviewed-on: http://git-master/r/114758 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record shared bus backup rateAlex Frid
Added shared bus backup rate entry to clock descriptor; initialized it for cbus (currently the only shared bus with backup source). Bug 1005576 Change-Id: I8124aa87f1dc307e42417da8f78797cfaf71e5dc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110934 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bc5ed688929c3c0ca920b5e9663cf9c6fb85c00f) Reviewed-on: http://git-master/r/114757 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Adjust Tegra3 cpu to emc ratioAlex Frid
On Tegra3 changed cpu rate threshold for maximum emc rate request from 750MHz to 925MHz. Adjusted cpu frequency table to provide entries close to the new threshold for all Tegra3 skus. Bug 998044 Bug 1003521 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I6e6df1958db9d55ad64cf35a5e9fe6ec74b8d4ea Reviewed-on: http://git-master/r/106946 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-12arm: tegra: kai: fix time does not increase in lp0Chandler Zhang
time does not increase in LP0 because GPIO4 is configured as POR. Change to active_low and pull push to fix the issue. Bug 1014548 Change-Id: I13c65ac6a4f3ae9158c58922e1ad6982f24bb103 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/114866 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Jinyoung Park <jinyoungp@nvidia.com> Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
2012-07-12ARM: Tegra: cardhu: No longer invert backlight on PM313Graziano Misuraca
Backlight value was inverted for panels with PM313. This assumed the panel was the 15", but because the 10.1" (AUO) is more prevalent and doesn't have the inverted backlight signal we no longer need to invert it. Note this will fix the backlight issue for AUO E1198 boards but break it for 15". Bug 962636 Reviewed-on: http://git-master/r/#change,93965 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Change-Id: Icb65592eb2df21e349e5a759a780e4438a0f5b26 Reviewed-on: http://git-master/r/95728 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11arm: tegra: pm269: 12.75mhz emc rateWen Yi
Add 12.75mhz emc frequency for Samsung K4P8G304EB-FGC2 LPDDR2 1GB memory chip. Bug 1011100 Change-Id: Ibbbb3f002c36c31cd2806051803ddd3ba9daa63b Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit a37cb14dc441005ddd977b6a83f41df817179d79) Reviewed-on: http://git-master/r/113383 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11arm: tegra: cardhu: move VI to PLL_PJihoon Bang
As a part of effort to bring in 437MHz clock frequency in EMC, We need to move VI from PLL_M to PLL_P. Bug 1005576 Signed-off-by: Jihoon Bang <jbang@nvidia.com> Reviewed-on: http://git-master/r/112704 (cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835) Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e Reviewed-on: http://git-master/r/114241 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11ARM: tegra: iovmm: Allow alloc_client to take struct deviceHiroshi DOYU
Allow tegra_iovmm_alloc_client() to take struct device * instead of const char *name w/ __tegra_iovmm_alloc_client(). This is necessary to support IOVMM and IOMMU simultaneously. Change-Id: I18df5001bfe0ece8f9f15b636eb11def9f228dfb Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114215 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GARTVandana Salve
Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to deal with SMMU/GART in unified manner. This is necessary for DMA mapping API to pass the appropriate IOMMU address for SMMU and GART in the same code in nvmap. [Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.] Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee Signed-off-by: Vandana Salve <vsalve@nvidia.com> Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11arm: tegra: p1852: Add IOMMU_SMMU supportHiroshi DOYU
Migrating from IOVMM_SMMU to IOMMU_SMMU. Change-Id: If5bca4a3bce15d59641f11dfea3ad6da2a8efbf5 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-01 05:41:47 +0000