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2013-07-24mmc: tegra: 1.39V Tuning during device enumerationPavan Kunapuli
Tuning at 1.39V to find a valid tap value that works at all core voltages. Boosting emc clock to 900MHz before setting 1.39V and releasing the frequency after 1.39V setting is removed. Bug 1331018 Change-Id: Icbf009a90ba9d0bd88a5991aab2fad8f1783b823 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/252471 Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com> Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-07-24ARM: tegra: roth: Limit SD card clock to 82MHzPavan Kunapuli
Limiting SD card clock to 82MHz to ensure that the tap values obtained through tuning work with the full core voltage range even with boost mode enabled Change-Id: I562bb651d8eca8d412ea464cfbdca1b692783e55 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/252371 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-07-20ARM: tegra11: dvfs: Update T40T frequency limitsAlex Frid
Change-Id: I25851ce78f034ac592a0bd39ded1444f0a7e230d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/251056 GVS: Gerrit_Virtual_Submit Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-07-20ARM: tegra11: clock: Add c2bus floor sysfsXiao Bo Zhao
Change-Id: Ia3f1f5d1eb13944ec66db335abc29350a22da3df Signed-off-by: Xiao Bo Zhao <xiaoboz@nvidia.com> Reviewed-on: http://git-master/r/250896 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
2013-07-20ARM: tegra11: clock: Add emc and host1x sysfs floorsAlex Frid
Change-Id: Ia8bf319da85914e748c4a88877433e6c45667ef1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250565 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
2013-07-20ARM: tegra: clock: Add sysfs interface for bus floorsAlex Frid
Added mechanism to install sysfs objects for tegra shared bus floors. Currently no floor objects are installed. Change-Id: I20e1a1448ee799a5ec59087f3214b77a80c05408 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250564 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
2013-07-20ARM: tegra11: clock: Expand host1x shared busAlex Frid
Add cap, floor, and override shared users to host1x bus. Attached cap user to core cap interface. Change-Id: I20bf5f346f422d7f2cbd97a445f00847e8761ac8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250563 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Anshul Jain (SW) <anshulj@nvidia.com>
2013-07-20ARM: tegra11: clock: Re-factor host1x busAlex Frid
- Set host1x dev_id = "host1x" and con_id = NULL (these definitions were used before conversion of host1x to shared bus; during conversion ids were inadvertently swapped - restored now) - Renamed host1x bus shared users to be consistent with other shared buses Change-Id: Iecf1f27681658c69fc63ed71c99d62ae86d9f30b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250562 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Anshul Jain (SW) <anshulj@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra11: clock: Add host1x shared busAlex Frid
Change-Id: Ie63f856727f9ba9f93e6c75b7bd5fb80357448a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250561 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra: clock: Update emc monitor preset mechanismAlex Frid
- Allowed per-SoC code to select emc monitor preset rate. For now, rounded down boot rate is used as monitor preset rate (round down to not over-clock on boot). - Skipped emc clock update when monitor preset rate is set, but not yet enabled (to avoid temporary dip in EMC rate). EMC rate is updated only when monitor preset is enabled. - Preset EMC monitor rate after iso usage table is initialized. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/219504 (cherry picked from commit 9279fd450cba7c8012a405755d483dfc9b502941) Change-Id: I2b724df9dc95231d6a5760171aa18bd10bdb409a Signed-off-by: Xiao Bo Zhao <xiaoboz@nvidia.com> Reviewed-on: http://git-master/r/250525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-07-20ARM: tegra11: clock: Preset EMC monitor rateAlex Frid
Use EMC boot rate as EMC monitor output reading during initialization until actual monitoring starts. Bug 1239168 Change-Id: I64d397623eeafe459769db106d0bfe80223f654f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250524 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra: clock: Record boot rates for all clocksAlex Frid
Change-Id: Iea43edd693d1489aa87eff893a1cfcfca1379552 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250523 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra11: clock: Add cbus fine granularity regionAlex Frid
Added fine granularity region to cbus possible rates. In this region requested cbus rate is not clipped to dvfs steps, but rounded to fine granularity resolution. The latter is set as 12MHz, and the region is defined as 5 resolution steps below the top dvfs rate, assuming this top rate is reachable on the particular chip bin/sku. Change-Id: If1096ae068367819e64c55172c1a1c0a46c38b86 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250033 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra11: dvfs: Update T40T tables and limitsAlex Frid
Updated dvfs and edp tables, clock and voltage limits for T40T part. Change-Id: Ic256a6f3aa8026c96443ecc33204309275fcbe2e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250032 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra11: power: Add T40T core edp tablesAlex Frid
Change-Id: Id5c2163224cdb1c862ef708e0790d99e4f04775e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250031 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra11: dvfs: Don't throttle T40T nominal voltageAlex Frid
On T40T parts removed throttling of nominal voltage by boot core edp. Used the latter to specify detached mode (boot, disable, suspend) limits. Change-Id: Ifa846ec8c7cb79df91b80cc81ffdef0f02a45372 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250030 GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-20ARM: tegra: dvfs: Decouple nominal and detached voltagesAlex Frid
DVFS rail nominal voltage is minimum voltage required to run all associated clocks at maximum allowed rates. DVFS rail can be detached from clocks during initial boot, on suspend entry/exit, or when voltage scaling is disabled. So far, rail voltage in any detached mode was set to nominal level. This commit introduced separate voltages for each detached mode. If any of these levels is not specified, backward compatible nominal voltage is used. Since, suspend voltage may now be different from nominal (below), it is important for dvfs to suspend after suspend edp rate caps are set, and resume before edp. Hence, priorities of dvfs suspend notifiers were adjusted accordingly. Change-Id: Id05e0b16f24dc7d28b1ee9e87afd63d98a9ab86e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250029 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Xiao Bo Zhao <xiaoboz@nvidia.com>
2013-07-02arm: tegra: roth: Enable FAST init mode for smps9daily-2013.07.29.2_rel-roth-mp-3-partnerdaily-2013.07.29.1_rel-roth-mp-3-partnerdaily-2013.07.29.0_rel-roth-mp-3-partnerdaily-2013.07.26.1_rel-roth-mp-3-partnerdaily-2013.07.26.0_rel-roth-mp-3-partnerAnshul Jain
Bug 1315200 Change-Id: If1bfc2a17d302f10b4d5439fa5e1ba5914b2fcc5 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/244113 Reviewed-by: Tao Xie <txie@nvidia.com> Tested-by: Tao Xie <txie@nvidia.com>
2013-06-21misc: issp: Add usb js recovery mechanismAnshul Jain
This change recovery the JS uC after USB resume failure by unloading USB, resetting uC from ISSP and then reloading USB Bug 1306389 Change-Id: I086636d4b7b91e3a2874f584fa6efbfd2cae6014 Signed-off-by: Michael Hsu <mhsu@nvidia.com> Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/240004
2013-06-18ARM: tegra: config: set panic timeout 5 secsJean Huang
Change-Id: I342d1f1505caedabaefa0b2f0eb5dccdf5046bca Signed-off-by: Jean Huang <jeanh@nvidia.com> Reviewed-on: http://git-master/r/239022 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Tao Xie <txie@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-05-24ARM: tegra: dvfs: Don't fail same level override requestAlex Frid
When new VDD_CORE override level is the same as the one already in place do not return error from the override API. Bug 1280293 Change-Id: Ic4393541308139c2ac9579acc8e2af47b144d521 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/225378 (cherry picked from commit cea34a24e79f8be40fa5aaf6a38992a0d54e705e) Reviewed-on: http://git-master/r/231750 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Matt Wagner <mwagner@nvidia.com>
2013-05-22ARM: tegra: board: disable the alignement fixSuresh Mangipudi
Disable the h/w alignment fix for T114 A02. Bug 1289107 Change-Id: I6d64e2de23d0358a2edbf3730e4f1b6a70f6903b Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-on: http://git-master/r/228649 Reviewed-on: http://git-master/r/231096 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Zu <pzu@nvidia.com> Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com> Tested-by: Peter Zu <pzu@nvidia.com>
2013-05-21arch: arm: tegra11: Disable wifi prepowerNitin Bindal
Wifi prepower logic is needed to support multiple wifi chip vendors so that we can load different wifi driver at run-time. Disable this flag for rel_roth as it uses only bcm43241 wifi chip. Bug 1280309 Change-Id: Ia1399c3fe003c6704a868f7646c011d0899e8ddf Signed-off-by: Nitin Bindal <nbindal@nvidia.com> Reviewed-on: http://git-master/r/230826 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-05-21ARM: tegra: roth: Mask HS200 mode supportPavan Kunapuli
Mask HS200 mode support for sdmmc4. In DDR50 mode for eMMC can support max clock of 52MHz. For Tegra sdmmc controllers, the host clock in ddr mode should be double that of the eMMC device. Taking into consideration the dvfs tables, limiting ddr mode clock to 51MHz to allow for lower core voltages to set even when sdmmc4 clock is ON. Bug 1287739 Change-Id: Ib04dce91d771ab5505dd67ea3a8d5c704d0b499e Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> (cherry picked from commit 3db4b21d8d5eb5a99dbcd3d660478a3a89ced104) Reviewed-on: http://git-master/r/230048 Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Matt Wagner <mwagner@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-05-21ARM: Tegra: Roth: Increase Drive Strength for 4KMatt Wagner
Increase by 30mV Bug 1278943 Change-Id: I554c281ca1f12cb7494516844f4fd72e1d4b03b1 Signed-off-by: Matt Wagner <mwagner@nvidia.com> (cherry picked from commit e61f283f9966358e68c7cdcd9ea26bbc7bbc18c3) Reviewed-on: http://git-master/r/230045 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-05-21video: tegra: dsi: Enable MIPI auto calibrationVineel Kumar Reddy Kovvuri
Implementation of DSI MIPI auto calibration Bug 1166307 Change-Id: Id4be420978b56d662d77c6d145f9e51dc881d159 Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com> Reviewed-on: http://git-master/r/229914 Reviewed-by: Matt Wagner <mwagner@nvidia.com> Tested-by: Matt Wagner <mwagner@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-05-17ARM: tegra: roth: Add force update to P2560Anshul Jain
This change will force update firmware on P2560, this is done to help with downgrading versions as required. Bug 1266521 Change-Id: I9121a75c108d8a79f496ed7686a34e7fce66a3ad Signed-off-by: Anshul Jain <anshulj@nvidia.com> (cherry picked from commit 428c5acf8cabde6d72a9eee98f98b2bdefc52f60) Reviewed-on: http://git-master/r/229466 Reviewed-by: Automatic_Commit_Validation_User
2013-05-16ARM: Tegra: Roth: Update DSI SettingsMatt Wagner
Fix v_front_porch, v_back_porch and pwr_ctrl settings Bug 1283232 Change-Id: Ic5f7fcd49977157bfe64e47a4b9fbcee42fa79d3 Signed-off-by: Matt Wagner <mwagner@nvidia.com> Reviewed-on: http://git-master/r/228540 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-05-16arm: roth: Add regulator for fuseShardar Shariff Md
Add vpp_fuse entry into ldo4 of palmas Bug 1286520 Change-Id: I2caad9d715f1ea8fc40335c93dc36f8c7107289b Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/227900 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-05-15ARM: Tegra: Roth: Update HDMI SettingsMatt Wagner
Update drive strengths to fix compliance issues Bug 1278943 Change-Id: I83f9340f4031b2a675ed748307f0abd0455f1e3c Signed-off-by: Matt Wagner <mwagner@nvidia.com> Reviewed-on: http://git-master/r/225026 (cherry picked from commit 45a7dd54a9565efd63537a16c2cfc6f2e9194c43) Reviewed-on: http://git-master/r/228126 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-05-13ARM: tegra: roth: Remove pm_flags settingsPavan Kunapuli
pm_flags should be set by the core/client driver if the card needs to be powered ON during suspend and full enumeration is not required in resume. These flags should not be set by default through platform data Bug 1281367 Change-Id: I2b3301e92ca25e5db93809fc2a727182ede7c92a Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/227043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Bindal <nbindal@nvidia.com> Tested-by: Nitin Bindal <nbindal@nvidia.com> Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-05-06arch: arm: roth: reduce didim aggressiveness for rothMitch Luban
Set aggressiveness to 1 and do faster backlight phase in. Bug 1276704 Change-Id: Ie9a17b5a42862a0804c4217ca0992514371b1d50 Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/224321 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-04-30ARM:tegra: Change touch_panel_id to tp_idXiaohui Tao
touch_panel_id is too long for command line. Change it to tp_id Change-Id: I1fd359e4092aa4befd1589042ffbe4844345a80f Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-on: http://git-master/r/223549 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-04-30ARM: Tegra: Roth: Update DVFS for P2560Sang-Hun Lee
Bug 1181038 Change-Id: I1bb349448106dcc30e7d7fd6d62bbe9dfd2f9f7f Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/223940 Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-04-30ARM: tegra: roth: Enable power_off_railrrajk
Turn off sdhci rails for SD card before rebooting the device. Bug 1222606 Bug 1242658 Change-Id: Iabff0e1ba54460365765bb64fc15fc35a941f8fe Signed-off-by: rrajk <rrajk@nvidia.com> Reviewed-on: http://git-master/r/224122 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2013-04-29ARM: Tegra: Roth: Use Tegra11 Pinmux HeaderMatt Wagner
We mistakenly used tegra30 instead of tegra11 pinmux header Bug 1277823 Change-Id: I7950127d2dc3110f2e2ea5684f2e79630b9df6a0 Signed-off-by: Matt Wagner <mwagner@nvidia.com> Reviewed-on: http://git-master/r/223684 Reviewed-by: Automatic_Commit_Validation_User
2013-04-29arm: increase command line size to 2048 bytesAlexandre Courbot
Bug 1280123 Change-Id: I21ae0ee8c261f438e9428778674b2cee283bb913 Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-on: http://git-master/r/223696 Reviewed-by: Ankit Pashiney <apashiney@nvidia.com> Tested-by: Ankit Pashiney <apashiney@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-04-27ARM: tegra11: clock: Fix boot over-clocking warningsAlex Frid
- Increase maximum rate for secondary PLLM output to the main PLLM output limit - Removed non supported sata clocks from the clock tree Change-Id: I208df494a41ed620937086feb0271cd1dc85a5b6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/201537 (cherry picked from commit c70f6b86b9f46226cc8fed5fa76ef1e05d315dd8) Reviewed-on: http://git-master/r/221417 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
2013-04-26ARM: Tegra: Roth: Remove Invalid Device InitMatt Wagner
Bug 1169149 Change-Id: Ib3367d9c7f45bb714bfab8015a0516f4c4b5da87 Signed-off-by: Matt Wagner <mwagner@nvidia.com> Reviewed-on: http://git-master/r/223020 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-04-25ARM: tegra: roth: ISSP configs and FW changeAnshul Jain
This change separates issp device configuration for p2454 and p2560 boards. This change also downgrades the JS firmware P2454 from v37 to v30. Also, it creates a node for p2560 with v37. Bug 1266521 Bug 1270341 Bug 1276644 Change-Id: Ibb4b59d48146b71a8dec83c2460716299f38a0fc Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/222599 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-04-24ARM:tegra: Add support to parse touch panel idXiaohui Tao
Support to parse touch panel id for kernel Bug 1253012 Change-Id: I902a1a63efc030cb4b4e82e7301c00027c8e950c Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-on: http://git-master/r/221647 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Collins <rcollins@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-04-24ARM:tegra: Modify to detect panel id and choose clkXiaohui Tao
TPK panel uses the external clock. Modify code to choose clock source based on the panel id. Bug 1253012 Change-Id: Ife85c2173693d339ef1f94cc4285009408975c44 Signed-off-by: Xiaohui Tao <xtao@nvidia.com> Reviewed-on: http://git-master/r/218964 Reviewed-by: Tao Xie <txie@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Robert Collins <rcollins@nvidia.com>
2013-04-24ARM: tegra: add volt-temp constraint mode control and apiDiwakar Tundlam
Bug 1270003 Bug 1270570 Change-Id: I3840a6655ec5f84411146c168e40981b60e2add1 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-on: http://git-master/r/219169 Reviewed-by: Automatic_Commit_Validation_User
2013-04-24Revert "ARM: tegra: roth: Mask SDR50,SDR104 modes for SD"Pavan Kunapuli
This reverts commit 48e77540489b412eef56efb9782957bc34adb1e5. Bug 1259286 Change-Id: I274dcfd4b728c2fcbb33afb40b0625296a51bb38 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/222049 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-04-23ARM: tegra: power: Re-factor core voltage cappingPavan Kunapuli
Re-factored core voltage capping APIs: - Collapsed set level and enable APIs into one set level interface; non-zero level automatically enables capping, and zero level disables capping. Attempt to apply new non-zero level before the previous one is disabled is rejected. - Added error reporting and propagation through api layers - Allowed to set cap voltage at nominal vdd core level even if voltage to frequency mapping is not ready (no clock rates are capped at nominal voltage, anyway). Core voltage capping APIs are not used by any kernel client (designated to vdd core override mechanism, yet to be added). Hence, function names and signatures changes are transparent, for now. User space vdd core capping sysfs nodes are not affected and kept backward compatible. Bug 1246712 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I66343c77e1bae337b8c829d98fb98dc75fc9a971 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/221526 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Tao Xie <txie@nvidia.com> Tested-by: Tao Xie <txie@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-04-23ARM: tegra: dvfs: Add VDD_CORE override mechanismAlex Frid
Added mechanism to fix and lock (override) VDD_CORE rail voltage at particular level. When override mode is entered, all scalable shared buses and bus users (memory, graphics cbus clocks, system bus clocks) are throttled to/below the rate safe at override voltage. Other clocks, however, continue to run at rates set by the respective drivers. Hence override voltage must be high enough to allow maximum rates of all core clocks outside shared buses. The lowest possible override level is determined by core dvfs tables, and the supported override range is defined accordingly. Attempt to set override voltage outside the range will fail, with the exception of level 0 that is interpreted as request to exit override mode. Override voltage cannot be changed if VDD_CORE is already locked: first override mode has to be exited via zero level request, and then a new override voltage can be set. No other override arbitration is provided. Bug 1246712 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I34975774fbf05025e06d9db2a0de74da7f31a73f Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/221525 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-04-23ARM: tegra: sdhci: Pass min,max vcore overridesPavan Kunapuli
Pass minimum and maximum vcore override voltages to be used during auto tuning. Bug 1246712 Change-Id: If7a7cde14524645f06d8a762df721aa0543de59b Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/221395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-04-23mmc: tegra: Set override voltages with dvfs APIsPavan Kunapuli
Set tuning override voltages using dvfs APIs rather than regulators. During boot, if the minimum override voltage cannot be set, schedule for retuning. Bug 1246712 Change-Id: I91acd10b748a9d828b172420999f3cceda26d218 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/221394 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Tao Xie <txie@nvidia.com> Tested-by: Tao Xie <txie@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com>
2013-04-22ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an ↵Bo Yan
extended period may not work correctly This workaround is for ARM errata 799270 which is applicable to Cortex-A15 up to revision R2P4. The workaround is to read from a device register and create a data dependency between this read and the modification of ACTLR. Change-Id: I26813f17a8a9c6a90446ddeb943ef318e3c69770 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/212770 (cherry picked from commit 2340401e2dec7228bcc5d9074c310d0146454736) Reviewed-on: http://git-master/r/221144 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
2013-04-22ARM: tegra114: Enable ARM errata 799270Bo Yan
bug 1195192 Change-Id: Ib5b0c73f42f73610ec78464dcf789e38d8cab927 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/212769 (cherry picked from commit b2fa463444ecde860549e3ef01a1b70087eba775) Reviewed-on: http://git-master/r/221143 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 17:41:40 +0000