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2020-07-10MLK-24369 ARM: imx: Add dummy soc id for imx6ulz liteJacky Bai
for i.MX6ULZ Lite, there is no dedicated SOC id for it, so add a dummy ID and identify it by checking the MARK bit in fuse. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-07-01MLK-24359 ARM: dts: Add the i.MX6ULZ Lite EVK board supportJacky Bai
The i.MX6ULZ Lite is full compatible with i.MX6ULL/ULZ, and only support 9x9 package. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-04-30MLK-23880 arm64: dts: imx8dx: refine the pcieb clocksRichard Zhu
- Refine the PCIe clocks for iMX8DX and iMX8QXP. - Correct the HSIO power domain name on iMX8QXP, otherwise, the peripheral clocks wouldn't be enabled. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit a2c09691aeafc818c287f25d69e53b6411d4ef26)
2020-04-25MLK-23275-2: ARM64: dts: freescale: fsl-imx8mn-ddr4-evk: correct ldo1/ldo2 ↵Robin Gong
voltage Correct ldo1/ldo2 voltage as below: ldo1 --NVCC_SNVS_1V8 ldo2 --VDD_SNVS_0V8 Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit d11796134f55d88b49d79bf25d6c42b677ff47bc) (cherry picked from commit 1c923bdd27021b011358f9422a6a18cbf30de491)
2020-04-25MLK-23275-1: ARM64: dts: freescale: fsl-imx8mm-evk: correct ldo1/ldo2 voltageRobin Gong
Correct ldo1/ldo2 voltage as below: ldo1 --NVCC_SNVS_1V8 ldo2 --VDD_SNVS_0V8 Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 6e1db954c1261c9a8a40f7c4e33f03173c4d05b6) (cherry picked from commit 8574922dd583141a332be58fe1656ee05c9e5dd4)
2020-03-26MLK-23681 arm64: dts: imx: enable pcieb on 8qm mek baseboardRichard Zhu
Based on imx_4.1x kernel, enable the PCIEB on i.MX8QM MEK baseboard. Regarding to the base board HW limitation(two Disable#) are not connected. Only the standard PCIe EP device is supported on PCIEB port. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit d0331d84e5a14d6e2520d04540d1e893d75bd678)
2020-02-25MLK-23233-4 arm64: dts: refine pcie dts and add the pcieax2 and pciebx1 usecaseRichard Zhu
Different usecase maybe used by customer, add the PCIEA two lanes and PCIEB one lane usecase into fsl-imx8qm-pcieax2pciebx1.dts. Refine the PCIE dts nodes, add the requrired HSIO peripheral clocks for different consumers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23233-2 dts: arm64: sata: add the clks into sata nodesRichard Zhu
To avoid potential dump when access the PHY and MISC CRR registers. Add the CRRS clocks into SATA node. The codes are merged back from 4.19 to 4.14 refer to MLK-21695. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-02-25MLK-23331 arm64: dts: imx8mn: Update settings according to latest datasheetAnson Huang
According to latest datasheet Rev.0.1, 03/2020, VDD_ARM does NOT have dependency on VDD_SOC, so below table in datasheet can be used directly for VDD_ARM: Clock Voltage 1.2GHz 0.85V 1.4GHz 0.95V 1.5GHz 1.0V For DDR4 EVK board, system runs at nominal mode, so GPU can ONLY run up to 400MHz. For LPDDR4 EVK board, system runs at over-drive mode, so GPU can run up to 600MHz. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit e619dfe015d96f9322b59f386e00167ec1aab321)
2020-02-17MLK-23326 arm64: dts: imx8mn-evk: Correct 1.2GHz OPP voltageAnson Huang
When running at OD mode, VDD_ARM can NOT be lower than VDD_SOC, overwrite the 1.2GHz OPP's voltage to be same as VDD_SOC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 77714128a1da83fbc516b41206574e2e62348dc8)
2020-02-11MLK-23292-2 arm64: dts: fsl-imx8dx-mek: Add JDI WUXGA LVDS panel supportLiu Ying
This patch adds JDI WUXGA LVDS panel support on the i.MX8DX MEK platform. The JDI WUXGA LVDS panel works in LDB split mode. fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts uses LDB1 channel0 as the channel to transmit odd pixels and LDB2 channel0 as the channel to transmit even pixels. fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts swaps the channels to transmit odd/even pixels. Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 31c6c62eff01b3288828f2e1b9ecf6ad9204b3c6)
2020-02-11MLK-23292-1 arm64: dts: fsl-imx8dx-mek: Add IT6263 LVDS2HDMI dual channel ↵Liu Ying
support This patch adds IT6263 LVDS to HDMI transmitter dual channel support. The transmitter works with LDB split mode. fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts uses LDB1 channel0 as the channel to transmit odd pixels and LDB2 channel0 as the channel to transmit even pixels. fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts swaps the channels to transmit odd/even pixels. Signed-off-by: Liu Ying <victor.liu@nxp.com> (cherry picked from commit 7cd2417af24b8f54d0b91f9b655211db79f63abb)
2020-02-11arch: arm64: dts: 8dx: Add dts file for dsi panel use-caseRobert Chiras
Create the fsl-imx8dx-mek-dsi-rm67191.dts in order to add support for the MIPI-DSI panel usecase with the Raydium RM67191 DSI panel. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-10MLK-23288 dts: arm64: imx8dx-mek: add tja1100 card support for enet2 portFugang Duan
Add tja1100 card support for enet2 port. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-10MLK-23286: arm64: dts: add ov5640 dts support for i.MX8DX MEKGuoniu.zhou
Add ov5640 dts support for i.MX8DX MEK board Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
2020-01-28MLK-23258-4 dts: SATA requires PCIE_A power domain to be ONRanjani Vaidyanathan
SATA driver write to regisers in the PCIE_A power domain and hence PCIE_A needs to be powered on even when ONLY SATA is enabled. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-23MLK-23258-3 dts: Fix PCIE suspend/resume issueRanjani Vaidyanathan
Fix the parent-child power domain dependency to handle different PCIE usecases. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2020-01-22MGS-5489: arm64: dts: imx8dx: update GPU memory settingXianzhong
The 8DX MEK only has 1GB DDR, update GPU memory as below: - set GPU MMU mapping size to 1GB (0x80000000-0xC0000000) - set GPU reserve size to 128MB Signed-off-by: Xianzhong <xianzhong.li@nxp.com> (cherry picked from commit 30efecdc1cef0fcff82f5cebd9823c61fee17e74)
2020-01-22MLK-23262-2 ARM64: dts: fsl-imx8dx-mek-rpmsg: delete gpio for type-c ss muxPeter Chen
There is no Type-C ss mux chip on imx8dx mek, so delete the related GPIOs. The rpmsg dts file fsl-imx8x-mek-rpmsg.dtsi includes another phandle typec_ptn5110 for rpmsg i2c, we need this change to delete it again. Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2020-01-22MLK-23262-1 ARM64: dts: fsl-imx8dx-mek: delete gpio for type-c ss muxPeter Chen
There is no Type-C ss mux chip on imx8dx mek, so delete the related GPIOs. Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
2020-01-17MLK-23247: arm64: dts: Add DTS files for DSP play on imx8dx mekShengjiu Wang
This file is almost same as the fsl-imx8qxp-mek-dsp.dts Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2020-01-15MLK-23243-3 arm64: dts: Add DTS files for iMX8DX MEK boardYe Li
Add iMX8DX MEK DTS file and its rpmsg DTS file, both re-use the common MEK board DTS files. The 8DX MEK only has 1GB DDR, so decrease its CMA size to 320MB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9ab7b42c2c99dc0e2dd7fafa5cb4cebd792aceaf)
2020-01-15MLK-23243-2 arm64: dts: Add new DTS fsl-imx8x-mek for MEK common nodesYe Li
Abstract the MEK board DTS nodes to common files fsl-imx8x-mek.dtsi and fsl-imx8x-mek-rpmsg.dtsi. So that we can share the board nodes between 8QXP and 8DX MEK DTS Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e1a4c61d3c0f9593ec0d2292cc4d510bcb59a01f)
2020-01-15MLK-23243-1 arm64: dts: imx8dx: Fix GPU clock rateYe Li
According to iMX8DX spec, the GPU and shader frequecy are both 372Mhz Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 2dd79af22fd753434b4213b11b799053cb9ec358)
2019-12-13MLK-23112-2 arm64: Update the SW workaround for i.MX8QM B0 ERR050104Nitin Garg
Fix the build break. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> (cherry picked from commit bfa2018721eb17c12129e3605c5c51c2af859fc3)
2019-12-12MLK-23112 arm64: Update the SW workaround for i.MX8QM B0 ERR050104Nitin Garg
The upper bits, above bit-35, of ARADDR and ACADDR buses within in Arm A53 sub-system have been incorrectly connected. Therefore ARADDR and ACADDR address bits above bit-35 should not be used. Hence downgrade instructions using higher address bits. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 1894c0ed972d04d790a742c67b330d8a5d57e54c)
2019-12-05HSM-24: arm64: dtx: imx8qxp: enable more seco MU usersStéphane Dion
Enable all SECO MUs and increase number of users on the first one. Signed-off-by: Stéphane Dion <stephane.dion_1@nxp.com> (cherry picked from commit 56099536022e7e66cfc932069aa4a4701d84aa0b) (cherry picked from commit 510c39be31b36a0a126a8be8b3bdfcf89c5ba334)
2019-12-05HSM-24 arm64: dtx: imx8qm: enable more seco MU usersStéphane Dion
enable all SECO MUs and increase number of users on the first one. Signed-off-by: Stéphane Dion <stephane.dion_1@nxp.com> (cherry picked from commit 2197e1f3a75fe9d9832cff3aa979aa4235a1e7a7) (cherry picked from commit a6eb7b28e99dd0c377299f737a0da7c0629589f0)
2019-12-05SHE-17 arm64: dts: imx8qm: enable first SECO MUStephane Dion
Enabling use of the first SECO MU on i.MX8QM Signed-off-by: Stephane Dion <stephane.dion_1@nxp.com> (cherry picked from commit 2b65b323254965b1d563e0aee80e18678d631b9d) (cherry picked from commit 5ff969719af8a80a8146fcbd856f5d28562c1081)
2019-12-05SHE-17 arm64: dts: imx8qxp: enable first SECO MUStephane Dion
Enabling use of the first SECO MU on i.MX8QXP Signed-off-by: Stephane Dion <stephane.dion_1@nxp.com> (cherry picked from commit b7865b23439de010187a211d1c283d6159807569) (cherry picked from commit 3536a8b7dcec79906e3b0221b1d144eb91abc55c)
2019-12-05SHE-17 soc: imx8: SECO MU driverStephane Dion
Driver to communicate with SECO over messaging unit. Expose a char device to user-space so user can write messages that will be sent to SECO and read messages received from it. Data that should be exchanged with SECO through shared memory are indicated to this driver through ioctl calls. Signed-off-by: Stephane Dion <stephane.dion_1@nxp.com> (cherry picked from commit eb721810fdc309b6a32a7a64c7686eaa6052cdc7) (cherry picked from commit db41bf52c2edf7c0936686d806eb4b2373b385a0)
2019-12-05SSI-87: soc: imx: secvio: Add support for SNVS secvio and tamper via SCFWFranck LENORMAND
The driver register an IRQ handle to SCU for security violation interrupt. When an interruption is fired, the driver inform the user. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2019-11-21MLK-22998-1 dt-bindings: Update SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit 6dcd0242ae Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-11-21MLK-23019 arm64: dts: imx8mn-evk: add the rpmsg and enable rpmsg audioRichard Zhu
Enable the RPMSG on iMX8MN LPDDR4 EVK platform, and verify the rpmsg audio feature. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-20MLK-23009 arm64: dts: imx8mn: Enable cpufreq support on imx8mn lpddr4 evkJacky Bai
Adding the arm supply & enable more setpoint to support cpufreq on i.MX8MN LPDDR4 EVK board. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2019-11-04MLK-22883 ARM64: dts: correct the off-on-delay for imx8mnHaibo Chen
Correct the properity from off-on-delay-us to off-on-delay. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2019-11-01ARM64: dts: freescale: imx8mm/imx8mn: correct sdma device node nameRobin Gong
Correct node name to align with the legacy sdma node name, so that Yocto could recognize it easy on all i.MX SOCs for the feature download sdma firmware. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 6da7efcf266d53081474a13f2e542ac5e30fee1a)
2019-10-24MLK-22824-4: ARM64: configs: defconfig: enable pca9450 by defaultRobin Gong
Add pca9450 support into defconfig. Signed-off-by: John Lee <john.lee@nxp.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2019-10-24MLK-22824-3: ARM64: dts: freescale: fsl-imx8mn-evk: add pca9450Robin Gong
Add pca9450 device node in board dts. Signed-off-by: John Lee <john.lee@nxp.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2019-10-17MLK-22765 arm64: dts: imx8mn: Add LPDDR4 EVK board supportAnson Huang
Add i.MX8MN LPDDR4 EVK board support, PMIC will be added later when kernel driver is ready, and cpu-freq ONLY supports 1.2GHz OPP as it needs PMIC driver to be ready for other OPPs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2019-09-18MLK-22137 ARM: imx_v7_defconfig: Enable more configsAnson Huang
Enable more kernel configs to support AWS Greengrass. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2019-08-30MLK-22484: ARM64: dts: Fix mem clock for asrcShengjiu Wang
The mem clock is used to access the register, if there is no mem clock defined, we should use the ipg clock instead, otherwise there will be kernel dump after system reboot. [ 3.010962] Kernel panic - not syncing: Asynchronous SError Interrupt [ 3.010964] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.19.35-05057-g2134d856e6b2 #2889 [ 3.010966] Hardware name: Freescale i.MX8QXP MEK (DT) [ 3.010968] Call trace: [ 3.010969] dump_backtrace+0x0/0x178 [ 3.010971] show_stack+0x14/0x20 [ 3.010972] dump_stack+0x8c/0xac [ 3.010974] panic+0x120/0x28c [ 3.010975] __stack_chk_fail+0x0/0x18 [ 3.010977] arm64_serror_panic+0x74/0x80 [ 3.010979] do_serror+0x68/0x130 [ 3.010980] el1_error+0x7c/0xdc [ 3.010982] _raw_spin_unlock_irqrestore+0xc/0x48 [ 3.010984] clk_core_disable_lock+0x28/0x38 [ 3.010985] clk_disable+0x1c/0x30 [ 3.010987] regmap_mmio_write+0x54/0x68 [ 3.010989] _regmap_bus_reg_write+0x14/0x20 [ 3.010990] _regmap_write+0x60/0xa8 [ 3.010992] regmap_write+0x48/0x70 [ 3.010994] fsl_asrc_probe+0x258/0x660 [ 3.010995] platform_drv_probe+0x50/0xb0 Why this issue only happen at kernel reboot, it is because the ipg clock is enabled in default after system reset, after used once, the ipg clock is disabled, then reboot system, the issue happen. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 3306d4381ac6db3dbb08f08a6c4aaf24dcdcf528)
2019-08-28MLK-22514 arm64: dts: imx8mm: Fix GPU axi/ahb ratesLeonard Crestez
On imx8mm gpu AXI should be 800m and AHB 400m but assigned-clock-rates incorrectly assigned 400m to AXI and left AHB at 800m. Fixes: e744bde4148b ("MLK-21700-4 arm64: dts: imx8mm: Consolidate composite assigned-clocks") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> (cherry picked from commit 26abaad783dd00ad33b635e99a385587c458cbaa)
2019-08-19MLK-22429 imx8mn: fix audio pll settingPeng Fan
The AUDIO PLL max support 650M, so the original clk settings violate spec. In order not to impact audio functionality, let's div the clk by 2. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> (cherry picked from commit 179126f225738d377d0b3d3cd9cf5c13c443c561)
2019-08-07MLK-22400-2: ARM64: dts: imx8mn: support rpmsg audio in imx8mnShengjiu Wang
Support rpmsg audio in imx8mn Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-08-07MLK-22340-1: Revert "MLK-20277-4: ARM64: fsl-imx8mm-evk-m4: enable sai3 with ↵Shengjiu Wang
wm8524" This reverts commit b49dff663e17302230556745e45eb51b94dc1f0c. M4 request to control the SAI3 for some customer want to use the SAI3 + WM8524 for rpmsg playback, so remove the WM8524 sound card in this dts Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2019-08-05MLK-22369-2 ARM: imx: Fix PMC module registers offsetAnson Huang
The latest reference manual (Rev.0, 06/2019) shows PMC0 and PMC1 have different register offsets, clean them up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit bf3af829c84dae9ed6f6599969bdfc0ab8e2bfb3)
2019-08-05MLK-22369-1 ARM: imx: Fix the offset for the PMC0 control registerFabio Estevam
The PMC0 control register is at offset 0x28, not 0x24. Fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 3707626d82c7f6a446f3290d26bf5f5ff251bffb)
2019-07-24arm64: dts: freescale: Disable the csi_bridge node in m4 dts on imx8mmJacky Bai
In M4 dts, the I2C3 is disabled by default, so the CSI camera sensor is disabled too. it is not necessary to keep csi_bridge node enabled anymore, just disable it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Anson Huang <Anson.Huang@nxp.com>
2019-07-23MGS-5051 Modify the GPU CLK from 500M to 600M for IMX8MN(815) boardMinjie Zhuang
At IMX8MN(815) we need to Increase GPU CLK frequency to match the overdrive mode. The SOC default setting is overdrive mode,and GPU 600M is corresponding to overdrive mode. Signed-off-by: Minjie Zhuang <minjie.zhuang@nxp.com>
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