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Aligned latest i.MX6 ICS 3.0.15 kernel to pick up latest media changes for
Camera support.
Signed-off-by: Jeff Kudrick <jeff.kudrick@freescale.com>
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Remove the p1003 platform data as we do not need
it now.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Shutdown the DCDC5V supply on system shutdown to avoid LVDS
being ON after shutdown. Also disable the Audio AMP to avoid
noise after shutdown.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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This is the initial Linux-3.0 kernel porting to iMX53 SMD
platform.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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sdma: bd is bufferable dma buffer, interrupt handler can not get correct
data after sdma script updated. Which will cause there is no interrupt
after failed period number times in the interrupt handler.
This is a workaround.
Signed-off-by: b02247 <b02247@freescale.com>
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board's reset will not reset the modem power on gpio
reset the 3g modem at kernel boot up to make sure
3g modem at reset state in system up
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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We found some wired crash in the SLUB managed list, but it's too wired to fix.
Althrough we found almost all ARM platform using SLAB,
maybe it's because it's not very stable on ARM platform,
so we change to SLAB too.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This reverts commit c0730e07456705269f3c9a4b0e625f7fd9ca375e.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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This reverts commit b49928de9c47839a681eae67513f37bc936372ea.
Conflicts:
arch/arm/mach-mx6/clock.c
arch/arm/mach-mx6/cpu_op-mx6.c
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Stepan found:
CPU0 CPUn
_cpu_up()
__cpu_up()
boostrap()
notify_cpu_starting()
set_cpu_online()
while (!cpu_active())
cpu_relax()
<PREEMPT-out>
smp_call_function(.wait=1)
/* we find cpu_online() is true */
arch_send_call_function_ipi_mask()
/* wait-forever-more */
<PREEMPT-in>
local_irq_enable()
cpu_notify(CPU_ONLINE)
sched_cpu_active()
set_cpu_active()
Now the purpose of cpu_active is mostly with bringing down a cpu, where
we mark it !active to avoid the load-balancer from moving tasks to it
while we tear down the cpu. This is required because we only update the
sched_domain tree after we brought the cpu-down. And this is needed so
that some tasks can still run while we bring it down, we just don't want
new tasks to appear.
On cpu-up however the sched_domain tree doesn't yet include the new cpu,
so its invisible to the load-balancer, regardless of the active state.
So instead of setting the active state after we boot the new cpu (and
consequently having to wait for it before enabling interrupts) set the
cpu active before we set it online and avoid the whole mess.
Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time. This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends. Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Enable deferred resume for mmc block device,
only resume the sdhc bus when the first request
come after system resume from suspend.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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The real power key defined will mark the KEY_POWER down event
in the device events record as it's gpio is always low.
This impact the workarounded power key VOL-, and it's first
down event will be dropped.
So just remove the real power key define.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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enable suspend counter driver by default.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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L2 cache clean is not necessary any more, already tested it on
Arik ARM2, Arik Sabre-SD and Rigel Sabre-SD board.
Signed-off-by: Anson Huang <b20788@freescale.com>
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For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Conflicts:
sound/soc/imx/Makefile
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On mx6dl, set ipu2_clk's parent from pll2_pfd_400M.
On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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add dma_alloc_writethrough function to dma_mapping.c
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID
Signed-off-by: Guillermo <b12356@freescale.com>
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* only happend on sabre-auto board,atheros sdio wifi card can't be used
after suspend/resume
* Fix by keeping sdio power at suspend.
Signed-off-by: justin.jiang <b31011@freescale.com>
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Added support for changing DDR frequency on MX6DL.
During system IDLE, DDR freq can drop down to 24MHz
if none of the devices that need high AHB frequency
are active.
Changed the DDR code to handle both MX6Q and MX6DL
DDR and IOMUX settings.
Fixed bug associated incorrect IRAM memory allocation
used to store DDR and IOMUX data.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add led-gpio control and trigger for sabresd
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Add led-gpio control and trigger for sabresd
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Enable ION and imx ION driver
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Remove the pmem device define.
Add ion allocator device support and memory reservation.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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This patch corrects LDB and HDMI IPU/IPU DI setting for
Android kernel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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In our code 3d sharder clock uses 3d core clock CCGR field as its
enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock
as 2d core clock, while disable 2d core clock, it will disable 3d
core by mistake.
To fix it, remove the enable bit setting of 3d shader clock in
clock.c file.
Signed-off-by: Larry Li <b20787@freescale.com>
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We do not use GPU pmem anymore, as all the graphic
memory allocation are go through gpu drivers, includes
surface buffers, camera buffers.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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iENGR00179574: MX6- Add bus frequency scaling support disable
SATA PHY defaultly
Enable PHY in the SATA initilization, make sure the SATA work well.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Conflicts:
arch/arm/kernel/traps.c
arch/arm/mach-mx6/board-mx6q_sabresd.c
arch/arm/mach-mx6/cpu.c
arch/arm/mach-mx6/system.c
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Conflicts:
drivers/cpufreq/cpufreq_interactive.c
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* Adjust the parameters, enlarge the eye diagram.
* Force to the PCIE GEN1 speed.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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change clock source explicitly by calling set_parent() function
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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change the PAD config for audio
Signed-off-by: b02247 <b02247@freescale.com>
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Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to
pll2_pfd_400M.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Fix the boot failure caused by:
8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab
MX6- Add bus frequency scaling support
There is no SATA on MX6DL. Accessing SATA PHYs early in the boot
process causes the system to crash.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c340ccfbc3d1ec6bc3d642ea2009c8e25247e4bc)
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This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.
To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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When system is going to enter WAIT mode, set PLL1 to 24MHz
so that ARM is running at 24MHz. This is a SW workaround for
the WAIT mode issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add MIPI DSI Display support on mx6 SabreSD board.
MIPI DSI needs pll3_pfd_540M clock source for 540MHz.
if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz.
So add command line option disable_ldb when using MIPI DSI display.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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add ssi dual-fifo info in sdma structure
Signed-off-by: Gary Zhang <b13634@freescale.com>
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* Bring up the PCIE on i.MX6 SD board
* Add the PCIE PHY access routines
* Wrapper the board related codes by register one
platform driver and data
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Update p2p script firmware address in plat-imx-dma.c for MX6Q.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Though mx6dl only has one IPU, it can still support two DIs.
So two LVDS or LVDS+HDMI should be supported.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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enable ONFI NAND feature by command line parameter "onfi_support"
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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Default SPI nor flash pin config is wrong, correct it for SabreSD RevB
Signed-off-by: Robin Gong <B38343@freescale.com>
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