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2018-09-27imx6ull-colibri.dtsi: change touch i2c parametersMax Krummenacher
Switch on 22 kOhm pull ups and lower the I2C frequency to around 40kHz to get a more reliable communication. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-09-27imx6qdl-apalis.dtsi: card detect pins: use pull up and hysteresisMax Krummenacher
The apalis has a 8 and 4 bit SD/MMC interface. Switch on a 100k pull up on the card detect pins for carrier boards which leave the pin floating. Switch on hysteresis in case the signal has slow rise or fall times. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-07-20arm: dts: correct VDDA in SGTL5000 for imx6 modules.Gerard Salvatella
On imx6 the SGTL5000 audio codec supply voltage is 3.3V and not 2.5V as might have been copied over from other modules. Output is slightly overamplified if the value is not corrected, which may lead to signal clipping. Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-07-20ARM: dts: Coibri iMX6ULL: use wdog HW signal for resetMax Krummenacher
The i.MX6 ULL's watchdog is used to reset the SoC on reboot. The watchdog is configured to use the SoC's internal reset signal which does not generate a reset pulse on nRESET_OUT. Change the watchdog configuration to use a SoC external HW signal. This will additionally change the 'Reset cause' message from U-Boot from WDOG to POR. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-26ARM: dts: imx6: mux SD/MMC CD and SPI CS explicitlyColibri-iMX7_LXDE-Image_2.8b3.111-20180627Colibri-iMX6_LXDE-Image_2.8b3.111-20180627Colibri-iMX6ULL_LXDE-Image_2.8b3.111-20180627Apalis-iMX6_LXDE-Image_2.8b3.111-20180626Stefan Agner
Use a pinmux configuration for SD/MMC card detect and SPI chip select instead of relying on reset/boot settings. There have been no adverse effects observed, but it seems sensible to mux the pads explicitly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-26colibri-imx7: defconfig: enable sound simple card driverMax Krummenacher
The device tree got changed to use the simple card driver, so enable it in the defconfig. While at it remove the IMX_SGTL5000 driver now replaced by the simple card driver. While at it remove the unused ESAI driver. While at it remove the unused CS42XX8_I2C codec driver. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-21Revert "ARM: dts: colibri-imx7: limit eMMC SDHC frequency to 100MHz"Stefan Agner
This reverts commit 5f60d82d38a8af8529d1493463e301e548595ccb. Several modules have issues with HS400 at 100MHz at room temperature but they seem to work fine at HS400 at 200MHz. Do not restrict frequency for now. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21dts: imx: colibri eval/iris: change pins to capacitive touch adapterMax Krummenacher
The Capacitive Touch Adapter is an interface board designed to easily connect the Capacitive Touch Display 7" Parallel to the Colibri Carrier boards which do not have PCAP connector yet available on board. Change the pins for interrupt and reset to those defined in the Capacitive Touch Adapter's datasheet. While at it remove the '#ifdef PCAP' in favour of disabled nodes. That way one can fixup the device tree in U-Boot to disable the pwm nodes and enable the connected touch controller. e.g. for a Colibri iMX6S/DL: Colibri iMX6 # setenv fdt_fixup 'fdt addr ${fdt_addr_r} && fdt resize && fdt set /soc/aips-bus@02100000/i2c@021a8000/atmel_mxt_ts@4a status okay; fdt set /soc/aips-bus@02000000/pwm@02080000 status disabled; fdt set /soc/aips-bus@02000000/pwm@0208c000 status disabled' Colibri iMX6 # saveenv Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-21dts: imx: fix M41T0 RTC compatible stringGerard Salvatella
Toradex Carrier boards use the ST M41T0 RTC (not M41T00). The RTC is almost the same, but the M41T0 needs some special handling in case the oscillator fails. Now that support for this difference is available, using the new compatible string to make use of it. Sync with commit 10e718b1c60c4e490e6972cfa58e97fcf5260685 Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21dts: add can-spi controllerGerard Salvatella
Synced with 558d378d522189ad68fcb00aff05fd134bf20924 Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21dts: update/add atmel mxtGerard Salvatella
Add mxt nodes to dts and gpio-reset functionality. Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21dts: enable hdmi also on asterGerard Salvatella
Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21dts: synchronize snvs node pathGerard Salvatella
Synchronize with commit fcfdb9c32075501e64751cc6a79fd91d15933692 Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21arm: Invalidate BTB on prefetch abort outside of user mapping on Cortex A8, ↵Marc Zyngier
A9, A12 and A17 In order to prevent aliasing attacks on the branch predictor, invalidate the BTB on CPUs that are known to be affected when taking a prefetch abort on a address that is outside of a user task limit. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a07373c8c365746583f25f49fee41b1bc0ff94b2) Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2018-06-21arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17Marc Zyngier
In order to avoid aliasing attacks against the branch predictor, some implementations require to invalidate the BTB when switching from one user context to another. For this, we reuse the existing implementation for Cortex-A8, and apply it to A9, A12 and A17. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked commit from efcd0e857a656bbd1c1da15ff984ad6402332c61) [jason: adapted to 4.9] Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
2018-06-21ARM: dts: imx7-colibri: prepare module device tree for FlexCANStefan Agner
Prepare FlexCAN use on SODIMM 55/63. Those SODIMM pins are compatible for CAN bus use with several modules from the Colibri family. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21ARM: dts: imx6qdl: Fix SPDIF regressionFabio Estevam
Commit 833f2cbf7091 ("ARM: dts: imx6: change the core clock of spdif") changed many more clocks than only the SPDIF core clock as stated in the commit message. The MLB clock has been added and this causes SPDIF regression as reported by Xavi Drudis Ferran and also in this forum post: https://forum.digikey.com/thread/34240 The MX6Q Reference Manual does not mention that MLB is a clock related to SPDIF, so change it back to a dummy clock to restore SPDIF functionality. Thanks to Ambika for providing the fix at: https://community.nxp.com/thread/387131 Fixes: 833f2cbf7091 ("ARM: dts: imx6: change the core clock of spdif") Cc: <stable@vger.kernel.org> # 4.4.x Reported-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Signed-off-by: Shawn Guo <shawnguo@kernel.org> (cherry picked from commit f065e9e4addd75c21bb976bb2558648bf4f61de6) This fix was correct, but overwritten by commit 833f2cbf7091099baee28136dc68678e974c0ac5. MLB (Media Local Bus) Clock is in fact not related to SPDIF according to the MX6Q Reference Manual. Tested playback and record on pulseaudio with 44.1kHz samples. Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-21arm: imx: gpc: do not poweroff M/F mix in suspendMax Krummenacher
The Colibri iMX6ULL 256MB crashes in resume if the M/F mix domain is powered down when suspending. With this workaround this does not happen. Crash looks as follows: root@colibri-imx6ull:~# echo +3 > /sys/class/rtc/rtc1/wakealarm; echo mem > /sys/power/state [ 52.800741] PM: Syncing filesystems ... done. [ 52.856715] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 52.865669] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 52.875024] Suspending console(s) (use no_console_suspend to debug) [ 52.950638] PM: suspend of devices complete after 68.211 msecs [ 52.952506] PM: late suspend of devices complete after 1.835 msecs [ 52.954292] PM: noirq suspend of devices complete after 1.757 msecs [ 52.954300] Disabling non-boot CPUs ... [ 52.954307] Turn off M/F mix! [ 52.955663] PM: noirq resume of devices complete after 1.222 msecs [ 52.956767] imx-sdma 20ec000.sdma: loaded firmware 3.3 [ 52.957669] PM: early resume of devices complete after 1.411 msecs [ 52.959140] gpmi-nand 1806000.gpmi-nand: use legacy bch geometry [ 53.005653] Suspended for 2.907 seconds [ 53.012207] PM: resume of devices complete after 54.507 msecs [ 53.073751] Restarting tasks ... done. root@colibri-imx6ull:~# [ 55.049753] gpmi-nand 1806000.gpmi-nand: DMA timeout, last DMA :2 [ 55.056377] gpmi-nand 1806000.gpmi-nand: Show GPMI registers : [ 55.062835] gpmi-nand 1806000.gpmi-nand: offset 0x000 : 0x00000000 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-06-21ARM: dts: imx: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> (cherry picked from commit 3e1b857786f0d46a92b3a4d7878767883ed90bdc)
2018-06-21ARM: dts: imx6: add required RS-485 propertiesStefan Agner
To operate RS-485 on Toradex Carrier Boards a low active RTS signal is required. Furthermore, a low active RTS signal requires the receiver to be active (this seems to be a hardware limitation of the i.MX UART). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-06-19Merge branch 'fslc_4.9-1.0.x-imx' into toradex_4.9-1.0.x-imx-nextMax Krummenacher
2018-03-23ARM: dts: imx6ull-colibri-eval-v3: remove duplicate nodesStefan Agner
Remove duplicate nodes introduced with the move to L4.9.11 release. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23arm: dts: apalis imx6: fix mipi-csi2 gpio assignmentMax Krummenacher
The new Apalis iMX6 Mezzanine board allows access to the MIPI-CSI2 interface from the evaluation board. The current device tree has different GPIO pin assignments for the camera reset and power pins. Change the pin assignment to use Apalis GPIO1 for reset and Apalis GPIO2 for power down. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23arm: dts: apalis imx6: add timings for new 10 inch lvdsMax Krummenacher
Add timings for LTTD1280800101-L4WH-CT1 panel used in the new Capacitive Touch 10.1" LVDS display. Note that the color mapping is to be set as follows: fsl,data-mapping = "spwg"; fsl,data-width = <24>; Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23arm: dts: apalis imx6: add reset controller for atmel mxt multitouchMax Krummenacher
The Atmel maXTouch multitouch controller driver does not control the reset line connected to the chip. Use a GPIO reset controller node to release the reset line and make the controller work. Note that both the reset controller's and the mxt mutitouch controller's node are set to disabled. Either change this in the dtsi source or fix this from U-Boot if you use an Atmel maXTouch multitouch controller. setenv fdt_fixup 'fdt addr ${fdt_addr_r} && fdt set /soc/aips-bus@02100000/i2c@021a0000/atmel_mxt_ts@4a status okay && fdt set /mxt-reset status okay' Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23ARM: imx: mach-imx7d: configure clock source per FEC instanceStefan Agner
Configure Ethernet clock source for each FEC instance individually. This allows to use different clock source setting for the two FEC controllers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-03-23ARM: imx: mach-imx7d: put external ethernet clock in error caseStefan Agner
Exit early in case General-Purpose Registers are missing. This makes sure that clock is always freed properly (clk_put). Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-03-23ARM: dts: imx7: add alias for Ethernet controllersStefan Agner
Add alias for Ethernet controllers. This allows code to determine id of controllers using of_alias_get_id. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-03-23ARM: dts: imx7-colibri: Specify cable detect as ID and VBUS pinMax Krummenacher
Commit 95c163471135 ("usb: chipidea: use of extcon framework to work for non OTG case") requires both pins to be specified (ID and VBUS pin) to work correctly. Fix the remaining dts. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23ARM: dts: imx6-colibri: Specify cable detect as ID and VBUS pinMax Krummenacher
Commit 95c163471135 ("usb: chipidea: use of extcon framework to work for non OTG case") requires both pins to be specified (ID and VBUS pin) to work correctly. Fix the remaining dts. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23ARM: dts: imx6ull-colibri: Specify cable detect as ID and VBUS pinMax Krummenacher
Commit 95c163471135 ("usb: chipidea: use of extcon framework to work for non OTG case") requires both pins to be specified (ID and VBUS pin) to work correctly. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-03-23Merge remote-tracking branch 'remotes/fslc/4.9-1.0.x-imx' into ↵Marcel Ziswiler
toradex_4.9-1.0.x-imx-next
2018-03-12Merge tag 'v4.9.87' into fslc_4.9-1.0.x-imxMax Krummenacher
This is the 4.9.87 stable release Conflicts: drivers/dma/fsl-edma.c
2018-03-11bpf, ppc64: fix out of bounds access in tail callDaniel Borkmann
[ upstream commit d269176e766c71c998cb75b4ea8cbc321cc0019d ] While working on 16338a9b3ac3 ("bpf, arm64: fix out of bounds access in tail call") I noticed that ppc64 JIT is partially affected as well. While the bound checking is correctly performed as unsigned comparison, the register with the index value however, is never truncated into 32 bit space, so e.g. a index value of 0x100000000ULL with a map of 1 element would pass with PPC_CMPLW() whereas we later on continue with the full 64 bit register value. Therefore, as we do in interpreter and other JITs truncate the value to 32 bit initially in order to fix access. Fixes: ce0761419fae ("powerpc/bpf: Implement support for tail calls") Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Tested-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11bpf, arm64: fix out of bounds access in tail callDaniel Borkmann
[ upstream commit 16338a9b3ac30740d49f5dfed81bac0ffa53b9c7 ] I recently noticed a crash on arm64 when feeding a bogus index into BPF tail call helper. The crash would not occur when the interpreter is used, but only in case of JIT. Output looks as follows: [ 347.007486] Unable to handle kernel paging request at virtual address fffb850e96492510 [...] [ 347.043065] [fffb850e96492510] address between user and kernel address ranges [ 347.050205] Internal error: Oops: 96000004 [#1] SMP [...] [ 347.190829] x13: 0000000000000000 x12: 0000000000000000 [ 347.196128] x11: fffc047ebe782800 x10: ffff808fd7d0fd10 [ 347.201427] x9 : 0000000000000000 x8 : 0000000000000000 [ 347.206726] x7 : 0000000000000000 x6 : 001c991738000000 [ 347.212025] x5 : 0000000000000018 x4 : 000000000000ba5a [ 347.217325] x3 : 00000000000329c4 x2 : ffff808fd7cf0500 [ 347.222625] x1 : ffff808fd7d0fc00 x0 : ffff808fd7cf0500 [ 347.227926] Process test_verifier (pid: 4548, stack limit = 0x000000007467fa61) [ 347.235221] Call trace: [ 347.237656] 0xffff000002f3a4fc [ 347.240784] bpf_test_run+0x78/0xf8 [ 347.244260] bpf_prog_test_run_skb+0x148/0x230 [ 347.248694] SyS_bpf+0x77c/0x1110 [ 347.251999] el0_svc_naked+0x30/0x34 [ 347.255564] Code: 9100075a d280220a 8b0a002a d37df04b (f86b694b) [...] In this case the index used in BPF r3 is the same as in r1 at the time of the call, meaning we fed a pointer as index; here, it had the value 0xffff808fd7cf0500 which sits in x2. While I found tail calls to be working in general (also for hitting the error cases), I noticed the following in the code emission: # bpftool p d j i 988 [...] 38: ldr w10, [x1,x10] 3c: cmp w2, w10 40: b.ge 0x000000000000007c <-- signed cmp 44: mov x10, #0x20 // #32 48: cmp x26, x10 4c: b.gt 0x000000000000007c 50: add x26, x26, #0x1 54: mov x10, #0x110 // #272 58: add x10, x1, x10 5c: lsl x11, x2, #3 60: ldr x11, [x10,x11] <-- faulting insn (f86b694b) 64: cbz x11, 0x000000000000007c [...] Meaning, the tests passed because commit ddb55992b04d ("arm64: bpf: implement bpf_tail_call() helper") was using signed compares instead of unsigned which as a result had the test wrongly passing. Change this but also the tail call count test both into unsigned and cap the index as u32. Latter we did as well in 90caccdd8cc0 ("bpf: fix bpf_tail_call() x64 JIT") and is needed in addition here, too. Tested on HiSilicon Hi1616. Result after patch: # bpftool p d j i 268 [...] 38: ldr w10, [x1,x10] 3c: add w2, w2, #0x0 40: cmp w2, w10 44: b.cs 0x0000000000000080 48: mov x10, #0x20 // #32 4c: cmp x26, x10 50: b.hi 0x0000000000000080 54: add x26, x26, #0x1 58: mov x10, #0x110 // #272 5c: add x10, x1, x10 60: lsl x11, x2, #3 64: ldr x11, [x10,x11] 68: cbz x11, 0x0000000000000080 [...] Fixes: ddb55992b04d ("arm64: bpf: implement bpf_tail_call() helper") Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11bpf, x64: implement retpoline for tail callDaniel Borkmann
[ upstream commit a493a87f38cfa48caaa95c9347be2d914c6fdf29 ] Implement a retpoline [0] for the BPF tail call JIT'ing that converts the indirect jump via jmp %rax that is used to make the long jump into another JITed BPF image. Since this is subject to speculative execution, we need to control the transient instruction sequence here as well when CONFIG_RETPOLINE is set, and direct it into a pause + lfence loop. The latter aligns also with what gcc / clang emits (e.g. [1]). JIT dump after patch: # bpftool p d x i 1 0: (18) r2 = map[id:1] 2: (b7) r3 = 0 3: (85) call bpf_tail_call#12 4: (b7) r0 = 2 5: (95) exit With CONFIG_RETPOLINE: # bpftool p d j i 1 [...] 33: cmp %edx,0x24(%rsi) 36: jbe 0x0000000000000072 |* 38: mov 0x24(%rbp),%eax 3e: cmp $0x20,%eax 41: ja 0x0000000000000072 | 43: add $0x1,%eax 46: mov %eax,0x24(%rbp) 4c: mov 0x90(%rsi,%rdx,8),%rax 54: test %rax,%rax 57: je 0x0000000000000072 | 59: mov 0x28(%rax),%rax 5d: add $0x25,%rax 61: callq 0x000000000000006d |+ 66: pause | 68: lfence | 6b: jmp 0x0000000000000066 | 6d: mov %rax,(%rsp) | 71: retq | 72: mov $0x2,%eax [...] * relative fall-through jumps in error case + retpoline for indirect jump Without CONFIG_RETPOLINE: # bpftool p d j i 1 [...] 33: cmp %edx,0x24(%rsi) 36: jbe 0x0000000000000063 |* 38: mov 0x24(%rbp),%eax 3e: cmp $0x20,%eax 41: ja 0x0000000000000063 | 43: add $0x1,%eax 46: mov %eax,0x24(%rbp) 4c: mov 0x90(%rsi,%rdx,8),%rax 54: test %rax,%rax 57: je 0x0000000000000063 | 59: mov 0x28(%rax),%rax 5d: add $0x25,%rax 61: jmpq *%rax |- 63: mov $0x2,%eax [...] * relative fall-through jumps in error case - plain indirect jump as before [0] https://support.google.com/faqs/answer/7625886 [1] https://github.com/gcc-mirror/gcc/commit/a31e654fa107be968b802786d747e962c2fcdb2b Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11x86/apic/vector: Handle legacy irq data correctlyThomas Gleixner
The backport of upstream commit 45d55e7bac40 ("x86/apic/vector: Fix off by one in error path") missed to fixup the legacy interrupt data which is not longer available upstream. Handle legacy irq data correctly by clearing the legacy storage to prevent use after free. Fixes: 7fd133539289 ("x86/apic/vector: Fix off by one in error path") - 4.4.y Fixes: c557481a9491 ("x86/apic/vector: Fix off by one in error path") - 4.9.y Reported-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11x86/speculation: Use Indirect Branch Prediction Barrier in context switchTim Chen
commit 18bf3c3ea8ece8f03b6fc58508f2dfd23c7711c7 upstream. Flush indirect branches when switching into a process that marked itself non dumpable. This protects high value processes like gpg better, without having too high performance overhead. If done naïvely, we could switch to a kernel idle thread and then back to the original process, such as: process A -> idle -> process A In such scenario, we do not have to do IBPB here even though the process is non-dumpable, as we are switching back to the same process after a hiatus. To avoid the redundant IBPB, which is expensive, we track the last mm user context ID. The cost is to have an extra u64 mm context id to track the last mm we were using before switching to the init_mm used by idle. Avoiding the extra IBPB is probably worth the extra memory for this common scenario. For those cases where tlb_defer_switch_to_init_mm() returns true (non PCID), lazy tlb will defer switch to init_mm, so we will not be changing the mm for the process A -> idle -> process A switch. So IBPB will be skipped for this case. Thanks to the reviewers and Andy Lutomirski for the suggestion of using ctx_id which got rid of the problem of mm pointer recycling. Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: ak@linux.intel.com Cc: karahmed@amazon.de Cc: arjan@linux.intel.com Cc: torvalds@linux-foundation.org Cc: linux@dominikbrodowski.net Cc: peterz@infradead.org Cc: bp@alien8.de Cc: luto@kernel.org Cc: pbonzini@redhat.com Link: https://lkml.kernel.org/r/1517263487-3708-1-git-send-email-dwmw@amazon.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11x86/mm: Give each mm TLB flush generation a unique IDAndy Lutomirski
commit f39681ed0f48498b80455095376f11535feea332 upstream. This adds two new variables to mmu_context_t: ctx_id and tlb_gen. ctx_id uniquely identifies the mm_struct and will never be reused. For a given mm_struct (and hence ctx_id), tlb_gen is a monotonic count of the number of times that a TLB flush has been requested. The pair (ctx_id, tlb_gen) can be used as an identifier for TLB flush actions and will be used in subsequent patches to reliably determine whether all needed TLB flushes have occurred on a given CPU. This patch is split out for ease of review. By itself, it has no real effect other than creating and updating the new variables. Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Nadav Amit <nadav.amit@gmail.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mel Gorman <mgorman@suse.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/413a91c24dab3ed0caa5f4e4d017d87b0857f920.1498751203.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11ARM: dts: LogicPD Torpedo: Fix I2C1 pinmuxAdam Ford
commit 74402055a2d3ec998a1ded599e86185a27d9bbf4 upstream. The pinmuxing was missing for I2C1 which was causing intermittent issues with the PMIC which is connected to I2C1. The bootloader did not quite configure the I2C1 either, so when running at 2.6MHz, it was generating errors at time. This correctly sets the I2C1 pinmuxing so it can operate at 2.6MHz Fixes: 687c27676151 ("ARM: dts: Add minimal support for LogicPD Torpedo DM3730 devkit") Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11ARM: dts: LogicPD SOM-LV: Fix I2C1 pinmuxAdam Ford
commit 84c7efd607e7fb6933920322086db64654f669b2 upstream. The pinmuxing was missing for I2C1 which was causing intermittent issues with the PMIC which is connected to I2C1. The bootloader did not quite configure the I2C1 either, so when running at 2.6MHz, it was generating errors at times. This correctly sets the I2C1 pinmuxing so it can operate at 2.6MHz Fixes: ab8dd3aed011 ("ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV") Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11KVM/VMX: Optimize vmx_vcpu_run() and svm_vcpu_run() by marking the RDMSR ↵Paolo Bonzini
path as unlikely() commit 946fbbc13dce68902f64515b610eeb2a6c3d7a64 upstream. vmx_vcpu_run() and svm_vcpu_run() are large functions, and giving branch hints to the compiler can actually make a substantial cycle difference by keeping the fast path contiguous in memory. With this optimization, the retpoline-guest/retpoline-host case is about 50 cycles faster. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jim Mattson <jmattson@google.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: KarimAllah Ahmed <karahmed@amazon.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kvm@vger.kernel.org Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/20180222154318.20361-3-pbonzini@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11KVM/x86: Remove indirect MSR op calls from SPEC_CTRLPaolo Bonzini
commit ecb586bd29c99fb4de599dec388658e74388daad upstream. Having a paravirt indirect call in the IBRS restore path is not a good idea, since we are trying to protect from speculative execution of bogus indirect branch targets. It is also slower, so use native_wrmsrl() on the vmentry path too. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jim Mattson <jmattson@google.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: KarimAllah Ahmed <karahmed@amazon.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kvm@vger.kernel.org Cc: stable@vger.kernel.org Fixes: d28b387fb74da95d69d2615732f50cceb38e9a4d Link: http://lkml.kernel.org/r/20180222154318.20361-2-pbonzini@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11ARM: kvm: fix building with gcc-8Arnd Bergmann
commit 67870eb1204223598ea6d8a4467b482e9f5875b5 upstream. In banked-sr.c, we use a top-level '__asm__(".arch_extension virt")' statement to allow compilation of a multi-CPU kernel for ARMv6 and older ARMv7-A that don't normally support access to the banked registers. This is considered to be a programming error by the gcc developers and will no longer work in gcc-8, where we now get a build error: /tmp/cc4Qy7GR.s:34: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_usr' /tmp/cc4Qy7GR.s:41: Error: Banked registers are not available with this architecture. -- `mrs r3,ELR_hyp' /tmp/cc4Qy7GR.s:55: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_svc' /tmp/cc4Qy7GR.s:62: Error: Banked registers are not available with this architecture. -- `mrs r3,LR_svc' /tmp/cc4Qy7GR.s:69: Error: Banked registers are not available with this architecture. -- `mrs r3,SPSR_svc' /tmp/cc4Qy7GR.s:76: Error: Banked registers are not available with this architecture. -- `mrs r3,SP_abt' Passign the '-march-armv7ve' flag to gcc works, and is ok here, because we know the functions won't ever be called on pre-ARMv7VE machines. Unfortunately, older compiler versions (4.8 and earlier) do not understand that flag, so we still need to keep the asm around. Backporting to stable kernels (4.6+) is needed to allow those to be built with future compilers as well. Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84129 Fixes: 33280b4cd1dc ("ARM: KVM: Add banked registers save/restore") Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11ARM: mvebu: Fix broken PL310_ERRATA_753970 selectsUlf Magnusson
commit 8aa36a8dcde3183d84db7b0d622ffddcebb61077 upstream. The MACH_ARMADA_375 and MACH_ARMADA_38X boards select ARM_ERRATA_753970, but it was renamed to PL310_ERRATA_753970 by commit fa0ce4035d48 ("ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds"). Fix the selects to use the new name. Discovered with the https://github.com/ulfalizer/Kconfiglib/blob/master/examples/list_undefined.py script. Fixes: fa0ce4035d48 ("ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds" cc: stable@vger.kernel.org Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11x86/platform/intel-mid: Handle Intel Edison reboot correctlySebastian Panceac
commit 028091f82eefd5e84f81cef81a7673016ecbe78b upstream. When the Intel Edison module is powered with 3.3V, the reboot command makes the module stuck. If the module is powered at a greater voltage, like 4.4V (as the Edison Mini Breakout board does), reboot works OK. The official Intel Edison BSP sends the IPCMSG_COLD_RESET message to the SCU by default. The IPCMSG_COLD_BOOT which is used by the upstream kernel is only sent when explicitely selected on the kernel command line. Use IPCMSG_COLD_RESET unconditionally which makes reboot work independent of the power supply voltage. [ tglx: Massaged changelog ] Fixes: bda7b072de99 ("x86/platform/intel-mid: Implement power off sequence") Signed-off-by: Sebastian Panceac <sebastian@resin.io> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/1519810849-15131-1-git-send-email-sebastian@resin.io Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11x86/xen: Zero MSR_IA32_SPEC_CTRL before suspendJuergen Gross
commit 71c208dd54ab971036d83ff6d9837bae4976e623 upstream. Older Xen versions (4.5 and before) might have problems migrating pv guests with MSR_IA32_SPEC_CTRL having a non-zero value. So before suspending zero that MSR and restore it after being resumed. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jan Beulich <jbeulich@suse.com> Cc: stable@vger.kernel.org Cc: xen-devel@lists.xenproject.org Cc: boris.ostrovsky@oracle.com Link: https://lkml.kernel.org/r/20180226140818.4849-1-jgross@suse.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-11parisc: Fix ordering of cache and TLB flushesJohn David Anglin
commit 0adb24e03a124b79130c9499731936b11ce2677d upstream. The change to flush_kernel_vmap_range() wasn't sufficient to avoid the SMP stalls.  The problem is some drivers call these routines with interrupts disabled.  Interrupts need to be enabled for flush_tlb_all() and flush_cache_all() to work.  This version adds checks to ensure interrupts are not disabled before calling routines that need IPI interrupts.  When interrupts are disabled, we now drop into slower code. The attached change fixes the ordering of cache and TLB flushes in several cases.  When we flush the cache using the existing PTE/TLB entries, we need to flush the TLB after doing the cache flush.  We don't need to do this when we flush the entire instruction and data caches as these flushes don't use the existing TLB entries.  The same is true for tmpalias region flushes. The flush_kernel_vmap_range() and invalidate_kernel_vmap_range() routines have been updated. Secondly, we added a new purge_kernel_dcache_range_asm() routine to pacache.S and use it in invalidate_kernel_vmap_range().  Nominally, purges are faster than flushes as the cache lines don't have to be written back to memory. Hopefully, this is sufficient to resolve the remaining problems due to cache speculation.  So far, testing indicates that this is the case.  I did work up a patch using tmpalias flushes, but there is a performance hit because we need the physical address for each page, and we also need to sequence access to the tmpalias flush code.  This increases the probability of stalls. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # 4.9+ Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-08Merge remote-tracking branch 'linux-fslc/4.9-1.0.x-imx' into ↵Stefan Agner
toradex_4.9-1.0.x-imx-next Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-03-08ARM: dts: imx6: use SNVS RTC labelStefan Agner
The SNVS RTC does not use an address in its node name anymore. Instead of using the full path, simply use the SNVS RTC label. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>