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2013-08-06arm: tegra3: change max current to 10000mA for T33Naveen Kumar S
6000mA is the max current for regular T30 SOCs. Conditionally changing it to 10000mA for T33 SOCs to avoid passing the command line parameter max_cpu_cur_ma=10000 explicitly. Bug 1166110 Change-Id: I453c8e128a6cf32f10e0f6e4a577b857d38d8e4d Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: http://git-master/r/245335 (cherry picked from commit 041279fc8d156013558273c8ba33ab718b7f924c) Reviewed-on: http://git-master/r/251202 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bryan Wu <pengw@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2013-08-06arm: tegra: fuse: add api for chip minor revisionNaveen Kumar S
Added function tegra_get_minor_rev() to return minor revision number of the chip. Bug 1166110 Change-Id: I087331433cabb35c05fa2ce0bd53013b6fb6624f Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: http://git-master/r/245330 (cherry picked from commit f29df745d2e97c0feb5f9c195202ca55041fa14c) Reviewed-on: http://git-master/r/251198 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bryan Wu <pengw@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-15arm: tegra11: config: disable HDCP for L4TJong Kim
HDCP are not used/tested in L4T. It simply generates a lot of meaningless i2c timeout messages and wastes CPU cycles. If needed, individual users may recompile kernel with HDCP enabled. bug 1264520 Change-Id: I9f23c6850a68c7db0613a737becc95607c7559e7 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/248090 (cherry picked from commit f72439306a30ce3fbbb184cbf43129a0ad1d7297) Reviewed-on: http://git-master/r/248728 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11arm: tegra: dalmore: add default hdmi panel modeJong Kim
Add default 640x480 hdmi panel mode. This HDMI mode is just a dummy for device probe to pass and finish dc/fb/fbcon registration. The actual mode will be detected by detect worker and programmed to the hw a little later during boot process. bug 1264520 Change-Id: Iad2e3dca1316b347abdc72d8ee8c73444ce368e2 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243979 (cherry picked from commit b44efdeeaa328cb19add0c8f6ef3fb10dc5829dc) Reviewed-on: http://git-master/r/248024 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11arm: tegra: dalmore: remove section mismatch gcc warning.Jong Kim
Remove section mismatch gcc warnings for dalmore. bug 1264520 Change-Id: Ic19bf04c89de5b9d8f08e702c84150f62c5381e5 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243978 (cherry picked from commit c94da7a824eee8f6df5f893c8a81d56011a51d8a) Reviewed-on: http://git-master/r/248020 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11ARM: tegra: dalmore: clear fb if bl fb not defined.Jong Kim
Clear primary framebuffer if bootloader framebuffer is not defined. (Some bootloader such as u-boot may not support LCD display and not supporting LCD in bootloader is purely customer's choice and the kernel display driver should survive such configuration). bug 1301464 bug 1264520 Change-Id: I919c7961e694461d6083510cdc51e3cd6bcac156 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243977 (cherry picked from commit 6e713daa1b729e341f682568a12bd0ef0249be72) Reviewed-on: http://git-master/r/248013 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11Revert "ARM: tegra: dalmore: clear fb if bl fb not defined."Matt Pedro
This reverts commit 439d56a1b2b266d127e021e037be8e30c89f33fb. Change-Id: I28c7bcf8ad556b6a784d0a00f793cb05e0f94576 Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/247981
2013-07-11Revert "arm: tegra: dalmore: remove section mismatch gcc warning."Matt Pedro
This reverts commit 9d1dfe8d12009d7a64e468ec04466f3e3b387149. Change-Id: I527b106733138e1f093b918d653fa936741cdee4 Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/247980
2013-07-11Revert "arm: tegra: dalmore: add default hdmi panel mode"Matt Pedro
This reverts commit ed037358021f408a895cec4be9b6643efe7bee97. Change-Id: Idd6d4904ace18ceb2cb29d66a7cb2e648ea1610f Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/247979
2013-07-11arm: tegra: dalmore: add default hdmi panel modeJong Kim
Add default 640x480 hdmi panel mode. This HDMI mode is just a dummy for device probe to pass and finish dc/fb/fbcon registration. The actual mode will be detected by detect worker and programmed to the hw a little later during boot process. bug 1264520 Change-Id: I79105b760499bb88aae3bc1a01172d31394d6300 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243979 (cherry picked from commit b44efdeeaa328cb19add0c8f6ef3fb10dc5829dc) Reviewed-on: http://git-master/r/247277 GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11arm: tegra: dalmore: remove section mismatch gcc warning.Jong Kim
Remove section mismatch gcc warnings for dalmore. bug 1264520 Change-Id: I880ec7d3846ece5f57881ee4f69281c9b91327b8 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243978 (cherry picked from commit c94da7a824eee8f6df5f893c8a81d56011a51d8a) Reviewed-on: http://git-master/r/247276 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-11ARM: tegra: dalmore: clear fb if bl fb not defined.Jong Kim
Clear primary framebuffer if bootloader framebuffer is not defined. (Some bootloader such as u-boot may not support LCD display and not supporting LCD in bootloader is purely customer's choice and the kernel display driver should survive such configuration). bug 1301464 bug 1264520 Change-Id: Ia37f1f9db08166509bf02673268180f277286dc2 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/243977 (cherry picked from commit 6e713daa1b729e341f682568a12bd0ef0249be72) Reviewed-on: http://git-master/r/247275 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2013-07-02arm: tegra11: config: disable wakelocks for L4TNaveen Kumar S
Wakelocks are not used in L4T. Disabling wakelock config macros in tegra11 L4T defconfig. Bug 1314808 Change-Id: I8016d2661db3190a0dba682da62a7659a282c8d2 Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: http://git-master/r/243501 (cherry picked from commit 119bd2ae76e4f0d6511f3be64e739b0b5013640d) Reviewed-on: http://git-master/r/244130 Reviewed-by: Kiran Adduri <kadduri@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2013-06-12ARM: tegra: pluto: set the MAX77665 OC alert currentXin Xie
bug 1298931 Change-Id: Iea46c10c53a1fe76d09d386f45f05f2da7de1d7d Signed-off-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/237770 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-06-12ARM: tegra: tegratab: pwm freq to 48MHzMin-wuk Lee
Bootloader PWM freq KHz is set to 48MHz and its parent is PLLP. If PWM frequency is set to different and lower one in kernel begin, a little flicker can be observed until pwm is configured by backlight device driver. Bug 1299402 Change-Id: I1ab1e0e97c952d908fe746a5d5caccfe0ddaa7c6 Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/236579 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-06-12arm: tegra: pluto: enable INA230/INA231/HPA01112 current sensingXin Xie
Note: HPA01112, INA230 and INA231 are similar devices and using the same driver. This patch will set correct calibration for the INA230 on Pluto platform based on the battery in-serial resistor value and max battery current. After this patch will can read back battery current and power correctly using the INA230. This patch also leave comment on how to enable the over-current(OC) throttling using the INA230 device. It is not enabled on the Pluto platform currently because MAX77665 is used for the OC throttling. bug 1298931 Change-Id: I37f40e0d3a9ca14314af4f7ee5a5007c5665581f Signed-off-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/235214 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-06-12ARM: tegra: PMU POWER off when boot with charger modeHyongbin Kim
Some charger detected as SDP but it fails enumeration because it is not PC-USB. In this case, it makes continuous reboot. power off in charger mode -> PMU reset -> VBUS poweron -> charger mode -> not detected charger-> power off in charger mode. Also, this change prevent continuous reboot in detecting charger error case. Bug 1242042 Bug 1304013 Change-Id: I086fa17ea912b745d9fa0cd21526b78a7215bb44 Signed-off-by: Hyongbin Kim <hyongbink@nvidia.com> Reviewed-on: http://git-master/r/236708 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
2013-06-12arm: dt: tegra: tegratab: Change OV5693 device nameFrank Chen
Change OV5693 device name from "camera" to "camera.5693". Bug 1301059 Change-Id: I5d6b88c1ae3d529deb4f6411a558bdb77e385b7f Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: http://git-master/r/237443 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yin-Chia Yeh <yyeh@nvidia.com> Reviewed-by: John Sasinowski <jsasinowski@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-06-12arm: tegra: tegratab: Change OV5693 device nameFrank Chen
Change OV5693 device name from "camera" to "camera.5693". Bug 1301059 Change-Id: I66714c952a3b539f683ab8f10df7938e01b7189a Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: http://git-master/r/237442 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yin-Chia Yeh <yyeh@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: John Sasinowski <jsasinowski@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-06-11arm: tegra: tegratab: enable wifi 32K clk per board revisionHarry Hong
wifi 32K clk source ERS(E1569) : clk_32k_out DVT1(P1640_A00) : clk3_out DVT2(P1640_A01) : PMIC 32K out bug 1297696 Change-Id: I54d31c66ad1f8c5bbe61798abc2039aa3bf85f9a Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/237553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Gabby Lee <galee@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Shawn Joo <sjoo@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-06-11ARM: tegra: set macallan sys EDP cap to 24WSivaram Nair
Change-Id: I292d92ed2abeda5fb2c821b8dc7437771d0a9cf7 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/237147 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra: config: update l4t defconfigBibek Basu
Enable TEGRA_PLLM_SCALED & TEGRA_CPU_DVFS for l4t kernel Bug 1304476 Change-Id: I235d4a0d056d400c741c0f451a4c15284bbc59fb Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/237115 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra: USB: Dynamic host load supportKrishna Yarlagadda
Enable platform data to load xhci dynamically when otg cable is connected Bug 1242148 Change-Id: I586f035ceedf49fb321242e7ac2e272620315d7a Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/234145 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-06-11ARM: tegra: tegratab: enable 32KHz clk of CLK32KG pinHarry Hong
P1640 A01 revision will use pmic 32KHz as wifi 32KHz clk input. Enable 32KHz clk of CLK32KG pin. bug 1286467 Change-Id: I7c46585d1456f9aab906d3341bf112af80b9c26a Signed-off-by: Harry Hong <hhong@nvidia.com> Reviewed-on: http://git-master/r/235338 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-06-11ARM: tegra: T114 wake source table updateBitan Biswas
Disable wake sources that are not known to be tested with T114 bug 1275273 Change-Id: I259b066fbc498378b1fbb4b1577c4bf973cc10b1 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/231926 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra: allow 1-to-many irq to wake mappingBitan Biswas
Problem: Current Tegra wake table does not allow same USB irq to be used for multiple wake sources. Fix: Changed tegra_irq_to_wake API to return multiple wake table indices bug 1275273 Change-Id: I72e6d83cb71de76e23ea9623b6fcae34091171bb Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/231921 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra: dalmore: VBUS/ID any level wake enableBitan Biswas
bug 1286802 Change-Id: I1386bae17578c3ca532a801a5a9d6ed1b139d57b Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/231919 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra: USB1 VBUS and ID ANY wake level supportBitan Biswas
This change enables wakeup from USB cable connect and disconnect for both device(VBUS) and host(ID) cables. - board platform data used to enable the implementation - chip specific wakeups source file added with new API needed to detect VBUS and ID cable connect state - chip specific API exposed to return the USB1_VBUS and USB1_ID wake indices bug 1286802 Change-Id: I59cfca82a907d33190a5bc92f33de5986fada43f Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/231918 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-06-11ARM: tegra: fix board id checkBibek Basu
Correct the logical check for board id Bug 1220745 Change-Id: Iddfcc795772fc1f0a7ba07d59b305999afb00118 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/237140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-06-11ARM: tegra11: dvfs: Override DFLL mode Vmin based on fuseAlex Frid
Override DFLL mode Vmin with 0.9V if designated fuse is set. Bug 1291764 Change-Id: I994619f48f5fc116341d90716b55ddaf932cfdd4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/237072 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra11: dvfs: Update CPU Vmax trip temperatureAlex Frid
Reduced CPU Vmax trip temperature to account for hotspot characterization offset. Bug 1233302 Change-Id: I6021df285bd2d743324d9d6ffd3bec9563143650 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/237070 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra11: clock: Expand host1x shared busAlex Frid
Add cap, floor, and override shared users to host1x bus. Attached cap user to core cap interface. Change-Id: I6d9a1c8ad7d890dfaf5c02297df6349ff18328f4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/237064 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-11ARM: tegra11: clock: Re-factor host1x busAlex Frid
- Set host1x dev_id = "host1x" and con_id = NULL (these definitions were used before conversion of host1x to shared bus; during conversion ids were inadvertently swapped - restored now) - Renamed host1x bus shared users to be consistent with other shared buses Change-Id: Id8963cf477315c56de930084ca842c42df535925 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/237063 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10arm: tegra: pluto: reduce panel init sequence delayVineel Kumar Reddy Kovvuri
updates the delays in panel init command sequence. Improves lp0 resume time. Bug 1288173 Change-Id: Ic513e5adfd73c00fe4cf82105721e2b4b0197f9e Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com> Reviewed-on: http://git-master/r/236617 Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-06-10arm: tegra: tegratab: set KB_COL1 input with internal PUSimon Je
To get hall sensor input on DVT A00, set KB_COL1 pin as gpio input with internal PU Bug 1296922 Change-Id: Ib0b6a3422c12598199cfaaf887c6dc3b6bfc2589 Signed-off-by: Simon Je <sje@nvidia.com> (cherry picked from commit 22c69c067a5e7e557caa242225ed6c301f7149c7) Reviewed-on: http://git-master/r/234871 Reviewed-by: Youngjin Kim <nkim@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-06-10arm: tegra: tegratab: enable clk_out_3Shawn Joo
enable clk_out_3 as default. it is source input clk for rtc_clk in Comm module for P1640 FAB A00. Bug 1278403 Bug 1286467 Change-Id: I421c5447246c4a024be68b27bcf6f9f31ad2bf5f Signed-off-by: Shawn Joo <sjoo@nvidia.com> Reviewed-on: http://git-master/r/226695 Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-06-10ARM: tegra{3,11}: config: Enable CMA & IOMMUHiroshi Doyu
Enabled CMA & IOMMU Change-Id: I54550f6bbcf67b1ff61126a75ec1e9e9014cc125 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/236725 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10ARM: dma-mapping: Add new API dma_ops->map_pages()Hiroshi Doyu
Add new API dma_ops->map_pages() for performance bug 1286500 Change-Id: Ib8bbcad53024225173be765358af03d0961f8af0 (cherry picked from commit 1e3b6ee46a5defaa8e1fcc97fc5d9b619c481c41) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234137 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10ARM: dma-mapping: Round-up IOVA map baseHiroshi Doyu
This is necessary for iova_alloc_at(). On high order allocation, the lower bit of base was ignored, and it returns incorrect IOVA address. bug 1286500 Change-Id: I0be96b97c8036f8a5bc1c35a1c85e04593021a2b (cherry picked from commit from 578a5333d43b2c9a78f0a234d391c2f8f5382b5d) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234136 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10video: tegra: nvmap: Add tegra_iovmm_vm_insert_pages()Hiroshi Doyu
Use ops->map_pages() for nvmap. bug 1286500 Change-Id: Ibaaf27a3c5cb4086561f1b4bcd40ebb5a40cd12c (cherry picked from commit c8453b97711a9af0d4913de16574fab6bf97d07c) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234135 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10ARM: dma-mapping: Add macro to_dma_iommu_mapping()Hiroshi Doyu
To build without CONFIG_ARM_DMA_USE_IOMMU bug 1286500 Change-Id: I1a6e385bd6b4039fcc37e120893b98e3ef590746 (cherry picked from commit 094c98e7c4346961b9ad7f741a5d3756c671a071) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234134 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10ARM: dma-mapping: Add arm_iommu_detach_device()Hiroshi Doyu
Need the counter part of arm_iommu_attach_device(). bug 1286500 Change-Id: I7663075ba56e0cf7a0762927247bfb5b884cd750 (cherry picked from commit 96425941ba18e0aa68e22cdd476bd3e521aa8256) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234133 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10iommu/tegra: smmu: Add Tegra errata 1053704 for some of Tegra SoCHiroshi Doyu
Add workaround of TEGRA_ERRATA_1053704 for some of Tegra SoC bug 1286500 Change-Id: I7d1a75b198051bc49eb7e14e4e7892eab9818f29 (cherry picked from commit fc688d6f91ae4250cb16274bc8b41875ead06b4e) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234132 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-10iommu/tegra: smmu: Add support Multiple ASIDHiroshi Doyu
"nvidia,memory-client" ID is used to find a map/asid. If those info isn't provided, a platform can specify it in a fixup table later. bug 1286500 Change-Id: Id6b2955013d33052e9071678b7c119adf35a019f (cherry picked from commit 659e185e19482e781ae4be847aba12319a7da842) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/234117 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-06-08ARM: tegra: config: tegratab: enable POWER_SUPPLY_EXTCON configLaxman Dewangan
The power supply notification is from the power_supply extcon driver which receive the cable type information from USB driver. Enabling the config to enable the driver. bug 1304013 Change-Id: I88b724ee85cb670cbcb24266c99babf13231efcf Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/236783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
2013-06-08ARM: tegra114: Remove the wrong EMC_REFRESH write.Bo Yan
'1' is written into EMC_REFRESH in SDRAM self-refresh exit sequence. This is wrong. Remove it. bug 1270351 Change-Id: I0180f5d36e5605f3c91905cdde4149a9b01b453a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/236471 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2013-06-08arm: tegra: soctherm: fix throttle period timingXin Xie
Throttling period register setting for the 'brief' mode is based on the soctherm clock running at 136MHz, we need adjust it if we running at different soctherm frequency. bug 1295404 Change-Id: Ic5a20d169cc8e0ba590268db38b18ec89c5d815f Signed-off-by: Xin Xie <xxie@nvidia.com> Reviewed-on: http://git-master/r/236434 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Rick Song <ricks@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-06-08ARM: tegra: macallan: Set max clk to 156MHz for sdR Raj Kumar
Setting max clock limit to 156MHz for sd. Adding sd as vdd_core voltage regulator client. Bug 1302349 Change-Id: I12774cc428d8c4ea8c4165ba18cd620d4c10f369 Signed-off-by: R Raj Kumar <rrajk@nvidia.com> Reviewed-on: http://git-master/r/236246 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-08ARM: tegra: dvfs: Change CL-DVFS tuning orderAlex Frid
Change CL-DVFS tuning order: when tuning low: tune dfll low, then tune target module trimmers low when tuning high: tune target module trimmers high, then tune dfll high (was complementary order in both cases above). Bug 1291764 Change-Id: Ic1a3850790089975e045cc9efcceb1dc06513b40 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/236146 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2013-06-08ARM: tegra11: dvfs: Update AP40 Vmin in DFLL modeAlex Frid
Minimum voltage in DFLL mode for AP40 sku is different (0.9V) from all other skus (1.0V) that share the same cpu dvfs tables. Updated AP40 Vmin respectively. Bug 1291764 Change-Id: I3f40f24bc68c376d18b09b2f55987c05164cc05d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/236135 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-22 20:35:17 +0000