| Age | Commit message (Collapse) | Author |
|---|
|
1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
|
|
In current linux BSP USB H1 driver default load before otg driver load,
which cause USBx not match the ehci controller number. like bellow:
root@freescale /sys/devices/platform/fsl-ehci.0$ ls
driver modalias pools power subsystem uevent usb2
root@freescale /sys/devices/platform/fsl-ehci.1$ ls
driver modalias pools power subsystem uevent usb1
Signed-off-by: make shi <b15407@freescale.com>
|
|
MTD partition for SPI-NOR was not aligned to 8K.
Replace its offset from MTDPART_OFS_APPEND to MTDPART_OFS_NXTBLK.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
|
|
USB does not work when plug in a usb device during system suspend. Under this
case, USB driver will be in low power mode, but WIE bit not be set if usb wake
up is not enabled.So there are only ID change interrupt no USB wakeup interrupt
after system resume.In current bsp, after system resume ID change status not be
clear,and ID change interrupt will continue happen, which cause the system busy.
No checking WIR bit if ID change interrupt happen when USB in low power mode to
fix this issue.
Signed-off-by: make shi <b15407@freescale.com>
|
|
Another patch changed caam_ipg_clk's CG to CG4 and this commit will
revert this change.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
Fix chip select for SPI-NOR and
remove flags for no writeable partition for weim nor and
SPI-NOR
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
|
|
Per hardware design, we can't set LDO bypass mode on Sabreauto board,otherwise,
system will can't reset,if cpu freq run in 400Mhz.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Currently, if we used LDO bypass, will set pfuze register by I2C bus to modify
voltage according to different cpu frequency, if I2C transfer error, we should
restore to old cpu frequency, not only in cpufreq driver but also cpufreq core.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
- must add a new config item to enable USB
CONFIG_USB_FSL_ARC_OTG=y
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
|
|
Didn't care about pu_regulator is enabled or not when regulator restore if some
regulator set failed.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
* Aline weim-nor partition layout with u-boot expected
offtsets
"bootloader" /dev/mtd0
"bootenv" /dev/mtd1
"kernel" /dev/mtd2
"rootfs" /dev/mtd3
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
|
|
* Aline spi-nor partition layout
* set correct chip-select value
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
|
|
Currently, we use pm_notifier to enter suspend/resume flow. But in the notifier
we only set cpufreq, didn't tell CPUFREQ core what the current cpufreq setting
now. So in the next time if CPUFREQ core find the current cpu frequncy is not
the value that CPUFREQ core want to set before. CPUFREQ core will force to set
the freqs.old with its own rule, which means the freqs.old will be MODIFYED
unexpectedly, and this will cause wrong loops_per_jiffy. We need add cpufreq_
notify_transition in the suspend/resume interface of cpufreq.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Forget submit some local change...
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
On Sabresd board design, the WDOG_B output to reset external pmic source from
GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,
we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the
related pins.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Restore back cpu freq and regulator if set fail.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
This patch add the fuse check for VPU_DISABLE feature. If the fuse
bit for VPU_DISABLE is 1, which means VPU is disabled, then we will
not register VPU device to the kernel.
Signed-off-by: Jason Liu <r64343@freescale.com>
|
|
Setting certain IOMUX settings on SD1 prevents the system from
entering suspend. These pins are already configured as GPIO, so
it does not help to reconfigure them during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
|
|
In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
Read "Disabled MLB" bit in OTP CFG2 to check if to enable mlb.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
We should use module_init as usb driver initialization entry point.
To avoid the following crash when sabreauto board bootup:
Unable to handle kernel NULL pointer dereference at virtual address 00000030
pgd = 80004000
[00000030] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 Not tainted (3.0.35-02249-g6493632-dirty #3070)
PC is at gpio_set_value_cansleep+0x20/0x34
LR is at mx6_usb_h1_init+0x68/0x188
pc : [<80251638>] lr : [<80010bd4>] psr: 20000013
sp : e4049f60 ip : 000000ef fp : 00000000
r10: 00000000 r9 : 00000000 r8 : e4049f8c
r7 : 80521f04 r6 : e4049f80 r5 : 80521f10 r4 : 80af53cc
r3 : 00000000 r2 : 00000001 r1 : 00000001 r0 : 00000000
Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 1000404a DAC: 00000015
Process swapper (pid: 1, stack limit = 0xe40482f0)
Stack: (0xe4049f60 to 0xe404a000)
9f60: 80af53cc 80010bd4 00000001 02184200 0000004a 00000001 02184200 00000048
9f80: 00000001 0000004d 0000004a 00000001 0000004d 00000048 8002e020 80af4ac0
9fa0: 00000000 80010b6c 00000000 8003b4c4 00000000 80130000 00000000 80abf898
9fc0: 000001f0 8002e020 8002e564 80042040 00000013 00000000 00000000 00000000
9fe0: 00000000 800083cc 00000000 80008334 80042040 80042040 5104b14a f0e00000
[<80251638>] (gpio_set_value_cansleep+0x20/0x34) from [<80010bd4>]
(mx6_usb_h1_init+0x68/0x188)
[<80010bd4>] (mx6_usb_h1_init+0x68/0x188) from [<8003b4c4>]
(do_one_initcall+0x30/0x16c)
[<8003b4c4>] (do_one_initcall+0x30/0x16c) from [<800083cc>]
(kernel_init+0x98/0x144)
[<800083cc>] (kernel_init+0x98/0x144) from [<80042040>]
(kernel_thread_exit+0x0/0x8)
Code: e92d4010 e7933100 e1a02001 e1a00003 (e5931030)
---[ end trace 1b75b31a2719ed1c ]---
Kernel panic - not syncing: Attempted to kill init!
[<8004823c>] (unwind_backtrace+0x0/0xfc) from [<8051d790>]
(panic+0x74/0x19c)
[<8051d790>] (panic+0x74/0x19c) from [<80078ba8>] (do_exit+0x664/0x718)
[<80078ba8>] (do_exit+0x664/0x718) from [<80044fcc>] (die+0x250/0x2c8)
[<80044fcc>] (die+0x250/0x2c8) from [<8004ba74>]
(__do_kernel_fault+0x64/0x84)
[<8004ba74>] (__do_kernel_fault+0x64/0x84) from [<8004bc14>]
(do_page_fault+0x180/0x2e0)
[<8004bc14>] (do_page_fault+0x180/0x2e0) from [<8003b400>]
(do_DataAbort+0x34/0x98)
[<8003b400>] (do_DataAbort+0x34/0x98) from [<80040f10>]
(__dabt_svc+0x70/0xa0)
Some board for example sabreauto board usb power gpio is use a io
i2c expander gpio, gpio i2c driver load use subsys_initcall as driver
initialization entry point, so gpio is not accessible at early bootup.
Signed-off-by: make shi <b15407@freescale.com>
|
|
Change 996M setpoint voltage according to datasheet,
lower VDDARM_CAP from 1.275V to 1.25V, and VDDSOC/PU_CAP
from 1.275V to 1.175V.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
- remove mx6_usb_dr_init() in board specific initialization files
- Add module_init(mx6_usb_dr_init) and module_exit(mx6_usb_dr_exit)
in usb_dr.c to support the usb_dr modulization
- Export necessary function which is used in usb_dr.c
Signed-off-by: make shi <b15407@freescale.com>
|
|
MSL headfile part change
-Add and remove some function define in usb.h
Signed-off-by: make shi <b15407@freescale.com>
|
|
- Add USB_FSL_ARC_OTG configuration to imx6_defconfig and imx6s_defconfig,
the default configuration is selected as "y"
- add related USB_FSL_ARC_OTG configuration to Makefile
- add related USB_FSL_ARC_OTG configuration to Kconfig
Signed-off-by: make shi <b15407@freescale.com>
|
|
Enable SNVS config.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
1. Disable on-chip pull-up, pull-down, and keeper
2. Disable hysteresis
3. Speed = 100 MHz
4. Slew rate = fast
The optimizition make the bias point match the optimum point, which
can maximize design margin.
Signed-off-by: Fugang Duan <B38611@freescale.com>
|
|
Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
* Pass csi-tx slave address for adv7280 chipset
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
|
|
Add interface in header file to call sdma event pending trigger
function.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
|
|
Improve the board level suspend power by configuring
various IOMUX pads to low power state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
|
|
IPG_PERCLK is the parent of I2C. I2C needs a minimum of
12.8MHz as its input clock to achieve 400KHz speed. Hence
change the IPG_PERCLK speed accordingly.
MX6DQ/MX6DL - Set IPG_PERCLK at 22MHz (sourced from IPG_CLK)
MX6SL - Set IPG_PERCLK to 24MHz(Sourced from 24MHz XTAL).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
|
|
Configure MUX settings for bluetooth operation over UART3.
Enable RTS,CTS and DMA only for uart3.
Affected files :
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabreauto.h
arch/arm/mach-mx6/board-mx6solo_sabreauto.h
arch/arm/plat-mxc/include/mach/iomux-mx6q.h
On behalf of Francisco Munoz <francisco.munoz@freescale.com>.
Some modification are needed also on hciattach tool.
Signed-off-by: Israel Perez <B37753@freescale.com>
|
|
We must set the DMA mask for esdhc device.
To avoid the following crash when we do not have highmem pages:
[<c0044f90>] (__dabt_svc+0x70/0xa0) from [<c00cf460>]
[<c00cf460>] (mempool_alloc+0x3c/0x108) from [<c00f4aa4>]
[<c00f4aa4>] (blk_queue_bounce+0xc0/0x2fc) from [<c023761c>]
[<c023761c>] (__make_request+0x20/0x2b8) from [<c0235bb4>]
[<c0235bb4>] (generic_make_request+0x3b4/0x4cc) from [<c0235d74>]
[<c0235d74>] (submit_bio+0xa8/0x128) from [<c01279c4>]
[<c01279c4>] (submit_bh+0x108/0x178) from [<c012baa0>]
[<c012baa0>] (block_read_full_pag+e0x278/0x394) from [<c00cd520>]
[<c00cd520>] (do_read_cache_page+0x70/0x154) from [<c00cd64c>]
[<c00cd64c>] (read_cache_page_async+0x1c/0x24) from [<c00cd65c>]
[<c00cd65c>] (read_cache_page+0x8/0x10) from [<c014c354>]
[<c014c354>] (read_dev_sector+0x30/0x68) from [<c014dd4c>]
[<c014dd4c>] (read_lba+0xa0/0x164) from [<c014e300>]
[<c014e300>] (efi_partition+0x9c/0xed4) from [<c014ca0c>]
[<c014ca0c>] (rescan_partitions+0x15c/0x480) from [<c012f190>]
[<c012f190>] (__blkdev_get+0x324/0x394) from [<c012f300>]
[<c012f300>] (blkdev_get+0x100/0x358) from [<c023e5f4>]
[<c023e5f4>] (register_disk+0x140/0x164) from [<c023e73c>]
[<c023e73c>] (add_disk+0x124/0x2a0) from [<c03a7528>]
[<c03a7528>] (mmc_add_disk+0x10/0x68) from [<c03a7820>]
[<c03a7820>] (mmc_blk_probe+0x15c/0x20c) from [<c039cc90>]
[<c039cc90>] (mmc_bus_probe+0x18/0x1c) from [<c0294e28>]
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
|
|
1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
|
|
If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP.
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
|
|
Enable secure memory and sm test in defconfig.
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
Add Secure Memory and SNVS properties to MX6 configuration.
Previous configurations of MX6 platform device definition lacked
specific propeties for CAAM Secure Memory and SNVS. Added these
properties to define register ranges for both entities.
Also corrected the name for the offset of the address range for
CAAM Secure Memory to more accurately reflect it's purpose.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock
IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
|
|
not set wm8958 codec as builtin in imx6_defconfig
Signed-off-by: Gary Zhang <b13634@freescale.com>
|
|
There is 6% tolerance for PFM momde in standby so we need set 0.975V(>0.9V+%6)
for VDDSOC and VDDARM which maybe impact system resume ability.
Another two change is:
1.set VDDARM and VDDSOC standby voltage by setting PFUZE register directly,it
is not very friendly.So use more common "state_mem" in constrain of regulator
to set standby voltage.
2.align sabreauto code with sabresd
Signed-off-by: Robin Gong <b38343@freescale.com>
|
|
In mx6q arm2 board, the gpmi conflicts with SD module.
But the defconfig has enabled the gpmi by default.
So we have to add a kernel cmdline to enable the gpmi by hand in arm2 board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
|
|
Add scaling_available_freqs attribute in cpufreq for i.MX
can get cpufreq table info with:
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
996000 792000 396000
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
|
|
The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Signed-off-by: make shi <b15407@freescale.com>
|
