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This patch changes PWM frequency from 20KHz to 22KHz to workaround
unstable backlight issue when brightness is set to 253.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Adjust the adb/ums function initial sequence in MSL code,
to keep the windows .inf file unchanged to support ADB
with MI_01 configure.
Signed-off-by: Xinyu Chen <Xinyu.chen@freescale.com>
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Bring this change from mx53 smd.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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When switch to PMIC RTC, it needs to enable the PMIC alarm IRQ, so
that PMIC can wakeup the sytem when system in suspend mode if a alarm
event occur, and mask the PMIC SEQ_RDY IRQ to avid some issue when doing
suspend/resume task
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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tzic_enable_wake() will also called when mx5 enter
lp mode.
Move it to suspend_enter function to reduce log.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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sometime kernel can't enter suspend because tzic can't be set.
but it without print any log, this log help people quick find
out the suspend failure caused by tzic.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Once power off the MX53SMD, the NVCC_SRTC will lost, so we could not
save the time if cut the power. For MX53 RevD, if the battery is online
the power for PMIC RTC is always on, so use PMIC RTC instead of MX53 SRTC
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM
for vpu driver.
The two ioctls can be used when user allocates working buffer
from user space, for exmaple, allocating it from pmem interface
on android, then register it to vpu driver.
Signed-off-by: Sammy He <r62914@freescale.com>
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dvfs will active during suspend, will cause system hang sometime.
disable it before system enter suspend and enable it after resume.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Disable the CONFIG_ZONE_DMA configure to disable
DMA zone, but keep NORMAL zone.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Change the pmem cache policy from noncache/nonbuffer to WT:
cache/nonbuffer.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Remove the normal zone by set CONFIG_DMA_ZONE_SIZE = 0.
Add pmem=<gpu size>,<vpu size> commandline for set
the GPU and VPU pmem size on boot.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add new VPU_IOC_REQ_VSHARE_MEM ioctl to request vmalloced share memory.
Signed-off-by: Sammy He <r62914@freescale.com>
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Do not take care of the MEM_TAG whoes size is 0.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Enable USB accessory function in default configure file.
Add accessory usb function to android usb platform device.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Remove AMD gpu mmu support as default
Add "fbmem=" kernel parameter to configure the fb0 buffer size
Reserve all buffers (pmem, gpu sharemem, fb) in second SDRAM back
Add check for HDMI primary to avoid reserve for fb1
fb1/2 buffers are reserved 1080p RGB565 triple by default
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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After enable DMA, GPS will keep report these DMA error:
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2050 sr2:508a
UART: DMA_ERROR: sr1:2050 sr2:508b
UART: DMA_ERROR: sr1:10 sr2:1083
UART: DMA_ERROR: sr1:50 sr2:1082
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2050 sr2:508a
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:2010 sr2:508b
UART: DMA_ERROR: sr1:50 sr2:1083
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Flush-to-zero mode will be enabled with RUN FAST mode.
This mode will replace denormalized numbers with 0,
that means we can not support denormalized range:
±1.18×10e-3 ~ ±1.4×10e-45
since VFP will convert them to 0.
But this float range is supported by Dalvik's java.lang API.
and the float MIN value defined in libcore is actually 1.4e-45f.
So we must disable run fast mode in kernel, which may bring
protential issues.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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It's found that L2 read data multiplexer select cycle decreased
from 2 to 1 cycle will cause kernel hang after decompress.
This cycle decrease patch is co-work with the uboot patch,
which dec the RALAT (DDR read additional latency) from 5 to 2,
but rejected by IC.
So we must fix this by keep L2 read data multiplexer
select cycle as default.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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enable ifstat and activity_stats in android defconfig.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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1. Add DDR self-refresh mode and float pin operation when system idle
For audio playback use case on android r10.3, it can save 10mA@1.54V
about 15mW on DDRIO+ memory power, and 6.6mA@2.5V -16.5mW on VDD_REG
It can reduce more memory power consumption if cpu idle time is longer
2. remove the L1/L2 cache operation during suspend for mx53
The L1/L2 cache are powered by VDDA/VDDAL1 and they should be supplied
according to iMX53 datasheet, there is also no EMPG on MX53,
so it can be removed to improve system performance and power.
3. remap the suspend_iram_base as MT_MEMORY_NONCACHED instead of MT_HIGH_VECTORS
If the IRAM page is marked as Cacheable, the ARM cache controller will
attempt to flush dirty cache lines to DDR, so it can fill those lines with
IRAM instruction code. The problem is that the DDR is in self-refresh mode
and HighZ DDR IO PADs during system idle or suspend, so any DDR access
causes the ARM MPU subsystem to hang.
It needs to cherry-pick two patches(5a4aeb9f6,7c8d972d8) from community.
4. Add DDR self-refresh mode and float pin operation for mx53 ARD board,
and mx53 QS/Ripley board
This patch can resovle ramdom suspend/resume issue, since the early code
didn't consider the TLB missing case during suspend. It needs to save all
the M4IF/IO MUX registers firstly to make sure the page table entried into
TLB, and then enter DDR self-refresh mode.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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The commit f1a2481c0 sets up the default flags for MT_MEMORY and
MT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly
set as default for these entries so remove it. Also adding
the 'L_PTE_WRITE' flag so that these pages become read-write
instead of just being read-only
[this stops them being exposed to userspace, which is the main
concern here --rmk]
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED
types so that at boot-up, we can map memories outside system memory
at page level granularity
Previously the mapping was limiting to section level, which creates
unnecessary additional mapping for which physical memory may not
present. On the newer ARM with speculation, this is dangerous and can
result in untraceable aborts.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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[ARM] Do not call flush_cache_user_range with mmap_sem held
We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.
Also, since we really can't be holding the mmap_sem while calling
flush_cache_user_range AND vma is actually unused by the flush itself,
get rid of vma as an argument.
Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106
Signed-off-by: Dima Zavin <dima@android.com>
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Set this clock closed by default, and open it when it is needed.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Fix the NULL pointer reference when there is no
struct mxc_pm_platform_data defines on MX5 machines.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Audio is broken if buffers are in external ram and the external
ram clock is turned off. To fix it:
* In platform data, ext_ram is replaced with two settings:
ext_ram_rx and ext_ram_tx which control whether the buffer
will be in iram or external ram.
* imx-pcm.c no longer hardwired to put all capture streams in
external ram.
* if IRAM is disabled in the defconfig or if iram_alloc fails,
then ext_ram_rx or ext_ram_tx are updated so they will
show whether the buffers were allocated in external ram
or iram.
* During audio playback or capture, enable external ram clock
if the buffer is in external ram.
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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restructure the pm suspend/resume routines as mxc_pm_platform_data,
so split the SOC pm routines from machine pm routines.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Enable VFPLite fast mode.
Enable caching NEON data within the L1/L2 data cache.
Enable PLD forwarding in L2.
Shorten the L2 data RAM read multiplexer select to one cycle.
Disable write allocate and it's combine in L2.
Enable L2 observes outer cacheability.
Set default Tag and Data RAM latency to 4 cycles.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Revert "mx51/3 clock: Fix bug of set low bus flag incorrectly"
This reverts commit f3cacf0dc77ca2d672dc5efd98b3b8b2ccd19f5e.
Revert "MX5x - Fix race condition in clock code"
This reverts commit 1825c60e77f22227899b04165e9bda4333c6ecbe.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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The lp_med_freq and lp_high_freq flag counter should not be
increased or decreased in the machine layer clock enable/disable routing.
They have already been moved into platform layer clock routings.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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This reverts commit b4ecab5fe8f3606e1d65b07b9c08d3caf2bd2490.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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There is possible race condition between enabling/disabling clocks
and the corresponding calls to change the bus frequencies.
Fix by ensuring that the flags used to change the bus frequencies
are set in a atomic context and before the bus frequency is
actually changed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch is used to remove the workaround "pull down
GPIO_9" to support reboot in mx53 SMD. Another workaround
is adopted into U-Boot to force warm reset as cold reset.
New workaround can support watchdog timeout in mx53 SMD
board.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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This pin was not set before, it seems default as input, so need to
set as output
Signed-off-by: Tu Chih Chieh <b32449@freescale.com>
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The HW automatically tries to clock gate APLL is all the PFDs
are disabled, resulting in a possible race condition since
the SW also tries to disable the APLL.
Fix by clearing the PFD disable MASK bits in APLL.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Random failures can occur if SDHC clk is below AHB_CLK. So
ensure that ahb_clk is atleast 66.5MHz when SDHC is active.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The system randomly hangs when exiting LPAPM mode on MX51.
The root cause of the issue because the parent of
periph_apm_clk cannot be changed when main_bus_clk is sourced
from it.
To fix the issue, we cannot use periph_apm_clk to source
main_bus_clk in LPAPM mode. Instead we need to divide down
PLL2 using dvfs_podf and use individual dividers to further
reduce other clocks in PLL2 domain.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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enable cgroup related config in android default config.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add fuse bit check for GPU/VPU.
Some boards may not have GPU/VPU. This can be controlled by fuse
bit.
Signed-off-by: Terry Lv <r65388@freescale.com>
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As imx_2.6.35 branch has backout one ENGR00151885 commit recently:
MX50 Add SW workaround for DPLL unlock HW issue on Android.
and pushed a new one, but imx_2.6.35_android did not do rebase. So
just use this commit to align this two branch for such commit.
Signed-off-by Xinyu Chen <xinyu.chen@freescale.com>
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1.add AVI and AIF support.
2.add edid 4-block reading support.(not test)
Signed-off-by: Jason Chen <b02280@freescale.com>
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Add the workaround that significantly reduces the occurrence of the
PLL1 unlock HW issue. For MX50, this workaround needs to be applied
in three places:
1. Suspend/resume code.
2. PLL1 set rate function.
3. PLL1 enable
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Change product id to fix some WinXP machine can't connect with ADB.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add the workaround that significantly reduces the occurrence of the
PLL1 unlock HW issue. For MX50, this workaround needs to be applied
in two places:
1. Suspend/resume code.
2. PLL1 set rate function.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch changes imx5_android_defconfig file
to support SATA defaultly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This Patch is fix for the reboot bug, our mx51,mx53 will hang after
reboot more then 20 times(100%).
We found this bug is caused by enable dvfs, so this patch disable
dvfs when system poweroff.
kernel panic log is like:
Kernel panic: (attached full logs)
MXC Watchdog # 0 shutdown
Restarting system.
Unable to handle kernel paging request at virtual address fffffffc
pgd = 99e54000
[fffffffc] *pgd=90ce6021, *pte=00000000, *ppte=00000000
Internal error: Oops: 817 [#1] PREEMPT
last sysfs file: /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state
Modules linked in:
CPU: 0 Not tainted (2.6.35.3-01072-gb754390 #1)
PC is at 0x99ce02bc
LR is at 0x84de7d4b
pc : [<99ce02bc>] lr : [<84de7d4b>] psr: 20000013
sp : 99ce1e68 ip : 00004076 fp : 00000000
r10: f9ffffff r9 : 00000068 r8 : 8003a104
r7 : 00000000 r6 : 0000203c r5 : 28121969 r4 : 00000000
r3 : ec860ad4 r2 : 00000000 r1 : 00000000 r0 : fffffffc
Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c5387d Table: a9e54019 DAC: 00000015
Process reboot (pid: 2484, stack limit = 0x99ce02e8)
Stack: (0x99ce1e68 to 0x99ce2000)
1e60: 00000000 00000000 80042690 8003aff0 00000000 28121969
1e80: 01234567 8003aa54 00000000 8007a438 00000000 99ce1ed4 980029d0 99ce1ed4
1ea0: 000508fb 99ce1f14 99ce0000 800ee880 00000000 800a6fc8 99ce1edc 980029d0
1ec0: 00000000 8009f6b8 0000000e 99ce1ef8 980029d0 00000000 00000000 99ce1f94
1ee0: 99ce0000 800ee880 00000000 800a5a9c 99ce1ef8 8009f7ec 00000001 00000000
1f00: 00000000 7fffffff 00000000 00000000 00000000 00000000 ffffffff 508fb800
1f20: 00000000 508fb7ff 00000000 99ce1f94 99ce0000 800ee880 00000000 8009f784
1f40: 508fb7ff 00000000 99ce1e8c 00000000 980029d0 99a21640 808c4d0c 800a00a0
1f60: 99a21800 99ce0000 99a21800 800ce5b4 0001b6dc 7e90caf4 00000001 00000024
1f80: 8003a104 99ce0000 00000000 800ee7ac 00000001 0001b6dc 7e90caf4 00000001
1fa0: 00000058 80039f80 0001b6dc 7e90caf4 fee1dead 28121969 01234567 00000000
1fc0: 0001b6dc 7e90caf4 00000001 00000058 00017047 00000000 00000000 00000000
1fe0: 0001b804 7e90ca88 6fd17763 6fd0c3ec 60000010 fee1dead 00000000 00000000
Code: 00000000 40000000 00000000 80039e90 (f4000000)
---[ end trace 7f263b4201ae9f59 ]---
Kernel panic - not syncing: Fatal exception
[<8003e578>] (unwind_backtrace+0x0/0xf0) from [<8046e83c>] (panic+0x6c/0xe0)
[<8046e83c>] (panic+0x6c/0xe0) from [<8003d420>] (die+0x2b4/0x304)
[<8003d420>] (die+0x2b4/0x304) from [<8003f3e8>] (__do_kernel_fault+0x64/0x84)
[<8003f3e8>] (__do_kernel_fault+0x64/0x84) from [<8003f5c8>]
(do_page_fault+0x1c0/0x1d4)
[<8003f5c8>] (do_page_fault+0x1c0/0x1d4) from [<800392c8>]
(do_DataAbort+0x34/0x94)
[<800392c8>] (do_DataAbort+0x34/0x94) from [<80039a2c>] (__dabt_svc+0x4c/0x60)
Exception stack(0x99ce1e20 to 0x99ce1e68)
1e20: fffffffc 00000000 00000000 ec860ad4 00000000 28121969 0000203c 00000000
1e40: 8003a104 00000068 f9ffffff 00000000 00004076 99ce1e68 84de7d4b 99ce02bc
1e60: 20000013 ffffffff
[<80039a2c>] (__dabt_svc+0x4c/0x60) from [<99ce02bc>] (0x99ce02bc)
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This patch is fixing the USB vendor id and power key setting on LOCO board.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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The patch based on the following consumption:
- PLL1 is already enabled when Linux boot up, this is true.
- PLL1 is working on 800Mhz on MX51
- PLL1 does not change during system up, keep 800Mhz
The patch will have the following side-effect
- suspend/resume will take more time
Before enter stop (WFI) mode
(1) switch DDR and ARM to PLL2
(2) Disable AREN bit to avoid PLL1 restart during MFN change)
(3) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179
thus the equation |MFN/(MFD+1)| < 1
(4) Manual restart PLL1
(5) Wait PLL1 lock
After CPU out of WFI
(6) Set PLL1 to 800Mhz with only change MFN to 60, others keep
(7) Wait MFN change complete by delay more than 4.6us,
(8) Switch DDR and ARM back to PLL1
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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