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2010-10-15[ARM/tegra] clock: tuned 2d busy hint for emc clk.tegra-10.9.3Alex Frid
Tuned recently added (commit 98b1475bce96ad088e4105a73d34f1cf803f2ee0) 2d busy hint level to reduce NV omxplayer video-playback power. Change-Id: Ic8f807e761e13cefed84a1fdaccb81e8c3c79535 Reviewed-on: http://git-master.nvidia.com/r/8473 Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2010-10-13[Android Camera]: ref count for i2c and gpioZhijun He
Code added to track i2c and gpio object types on NVRM reftracker. This can be used to release handles whenever a system crash happens. This can help properly shutdown and deinitialize imager peripherals. Bug 728160 Reviewed-on: http://git-master/r/5877 (cherry picked from commit 2661d755bfb401204cacafcc5f944085c19df627) Change-Id: Iae3d08ef0fa5ef21d1e243249caa386f2a37fc3a Reviewed-on: http://git-master.nvidia.com/r/8261 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2010-10-12[ARM/tegra] clock: added 2d busy hint for emc clk.Michael Frydrych
Bug 731173 (cherry picked from commit 8961b22287d3f7b6ea33744905675ebd2df236a2) Change-Id: Icc323fec5507991184b20fcb22e017d2acadd4e3 Reviewed-on: http://git-master/r/8127 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-10-12[ARM/tegra] RM: Restarted EMC digital dll.Alex Frid
Restarted EMC digital dll after EMC clock change. Bug 722440 Change-Id: Id8b0ea4381302eb9dec85757840587d782a7a793 Reviewed-on: http://git-master/r/8259 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-10-12[arm/tegra] Tristate pta pingroupHoang Pham
The pta pingroup is in NORMAL at POR. Tristating this pingroup at init by default to reduce the power when enter LP0 mode Bug 740749 Change-Id: I5ff86c3ddbeb5c608eaee9e11db462acff8ea222 Reviewed-on: http://git-master/r/8109 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2010-10-11[arm/tegra] gpio: Correcting pingroup of gpio M6 to ldiLaxman Dewangan
There was typo bug in the gpio-pingroup table where gpio M6 is configured for LD1 pingroup. Correcting table entry to configure GPIO M6 to pingroup LDI. Change-Id: I6938e3e7b28525a920c8a8c6eb59d7013c1f97d0 Reviewed-on: http://git-master/r/8182 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Martin Chi <mchi@nvidia.com> Tested-by: Martin Chi <mchi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-10-07[ARM/tegra] power: Fixed assert in suspend init.Alex Frid
Set correct field offset in assert on CPU power request polarity during suspend initialization. Bug 741736 Change-Id: Ie7c6589b47b92af815151f6d95ae0acd3030c9cc Reviewed-on: http://git-master/r/7794 Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-10-05[usb-host]Remove controller restart in host mode during resumeVenkat Moganty
During resume from LP0 controller is getting restarted in host mode due to this hcd state is getting changed from the suspend state. Controller state should not be changed for host mode. Fixed this to restart the controller only in OTG mode. Bug 724437 (cherry picked from commit cbea530301ae3d9a4a7271d11c819bfc8de8f892) Change-Id: Idc2897a2790087e00ee66e30fea734c9d117029e Reviewed-on: http://git-master/r/7833 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-10-05[arm/tegra] provide wifi power/carddetect abstractionRakesh Kumar
When user switches on wifi, wifi driver need to poweron wifi card and ask sdhci stack to enumerate the card. Sdhci stack does not provide any interface to achieve this. Major wifi vendors depend on platform to provide wifi poweron/reset/carddetect abstraction function. Bug ID 739374 Change-Id: I988393352ff6cb54be3d70a59c94f67eedff06fb Reviewed-on: http://git-master/r/7097 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Tested-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-10-02[arm/tegra] pmc: Overriding only kbc pins during suspend.tegra-10.9.2Laxman Dewangan
To enable dpd override of the kbc pins during suspend, it needs to write into dpd override register. By mistake, it was also resetting the other configuration bits. Fixing this issue. bug 739052 Change-Id: I06cf4a7252157418a4789281a79f79946d7f2bdc Reviewed-on: http://git-master/r/7500 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-10-01[ARM] ventana defconfig: V4L2 + UVC support addedBharat Nihalani
Adding this support to allow USB webcam verification on Ventana. Bug 722146 Change-Id: Id856ca674faf9cd663fcaf1042569c9b2d733aa8 Reviewed-on: http://git-master/r/7595 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-30[arm/tegra] kbc: Keep enabling if wake key configured in suspend/resume.Laxman Dewangan
Keep enabling the kc controller only if any of keys are configured as wakeup source during suspend. bug 735233 (cherry picked from commit 13825a46587b0508aa7a43054964b76524d5f2b6) Change-Id: I028965400ee4f96c1460f8e261a2376943384030 Reviewed-on: http://git-master/r/7499 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-30[tegra/config] ventana: Enabling CONFIG_I2C_CHARDEVLaxman Dewangan
Enabling the config variable CONFIG_I2C_CHARDEV to enable I2C device interface from user space. With enabling this, i2c-* device files will be found in /dev directory. This make it possible to use the user-space programs to use the I2C bus. bug 723618 Change-Id: Ib0702e02638f34089ff448b5f28ba8e999544612 Reviewed-on: http://git-master/r/7423 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-27[ARM/tegra] RM: Expanded CPU DVFS tables.Alex Frid
Expanded CPU DVFS tables to include AP25/T25 data. Dependency on tegra core commit 7fedffa609eaa8288b2db93068a88a509f5268df Bug 643434 Change-Id: I705e7373007aed0b524dda221f690162880fd585 Reviewed-on: http://git-master/r/7243 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-26[arm/tegra] ventana: Enabling CONFIG_ISL29018Laxman Dewangan
Enabling the config variable ISL29018 for enabling the driver for light sensor ISL29018. Change-Id: I676ba2493e8d590d379f81177ce8b036dd271a4d Reviewed-on: http://git-master/r/7196 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-24[ARM-tegra]UsbPhy: Enable Host mode context save in LP0Venkat Moganty
During LP0 suspend host mode context is not saved and this makes atatched device to re-enumerate after coming out of the LP0. To fix this USB context registers are saved during LP0 suspend and restored back on LP0 resume. Bug 721762 (cherry picked from commit c4ff3f80540e0228790ea568464b2a8078cce188) Change-Id: I2b57abcfc6451ceccc545c648c0182a6b81dec71 Reviewed-on: http://git-master/r/7185 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-24[arm/tegra] Putting IPv6 config dependenciesRahul Bansal
Putting in IPv6 Security related dependencies. Bug: 690020, 690023, 687255 Change-Id: Ie8fe292eca61657e1dad816126849872bd3f9111 Reviewed-on: http://git-master/r/7132 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-24tegra/bt wake : enabling bt wake sourceAnantha Idapalapati
enabling BT wake source to wake up the system from low power modes. Bug 680524, 691608 Change-Id: Icc63ab86616da302270325f9d4867834af645785 Reviewed-on: http://git-master/r/6854 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-24tegra bluesleep : enabling bluetooth active power management driver.Anantha Idapalapati
Bluesleep driver manages the power of BT chip. now enabling the driver in the default build of ventana. Bug 680524, 691608 (cherry picked from commit 9e75f8c8a105bc82f280eeed4284a1bf8779b048) Change-Id: Ied1c31a2f7f63eddf201bd7c82c116effa10deaf Reviewed-on: http://git-master/r/6852 Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-23tegra bluesleep: creating a bluesleep platform device.Anantha Idapalapati
Based on CONFIG_BT_BLUESLEEP configuration variable, a bluesleep device will be created and used to actively manage the BT device power. Bug 680524 Bug 691608 Change-Id: If2f470a385392ad7a94b6d69a919be55487569e9 (cherry picked from commit 011a705248274804c80c12af5366693e6662829b) Change-Id: If2f470a385392ad7a94b6d69a919be55487569e9 Reviewed-on: http://git-master/r/6851 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-23[odm] whistler pinmux: Fixing UartA pinmux option for RILLaxman Dewangan
RIL interacing with UARTA is using the 4 line. The correct configuration for this interface is Config6. Currently it is config1 which is causing the issue on other pin operation. Fixing this issue. bug 710711 Change-Id: I68e426de4597f87d832fb934e2cf6120e898b3de Reviewed-on: http://git-master/r/7100 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-23[ARM/tegra] ODM: Enabled EMC DFS for Elpida LPDDR2.Alex Frid
Enabled EMC DFS for Whistler E1112 board with Elpida LPDDR2. Change-Id: Id6a09e1b96120d44af95498d9c6ef8e3e318bb0b Reviewed-on: http://git-master/r/7044 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-23[arm/tegra] isl29018: Adding board info for isl29018.Laxman Dewangan
The isl29018 driver have moved from hwmon to iio and so config varaible name changed. Changing config name in board specific file. (cherry picked from commit 50bb444f37080936d94e0c99bdcec1756d254901) Change-Id: I6bed55c9e2bc907678e6ba927817d3f380cdb53b Reviewed-on: http://git-master.nvidia.com/r/7110 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-22[ARM/tegra] RM: Updated HDMI PLLC settings.Alex Frid
Changed PLLC settings to increase comparison and VCO frequency for 12MHz and 26MHz reference clocks. Kept PLLC settings unchanged for other reference clocks. Setup constant charge pump control for all HDMI PLL configurations. Bug 734868 Bug 719667 Change-Id: I6a34bbebc39042dbf9645cb84538eacf775eb8ff Reviewed-on: http://git-master.nvidia.com/r/6752 Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-21[ARM/Tegra] nvrm : Clean up user mode DMA handlesVictor(Weiguo) Pan
Nvrm exposes nvrm DMA APIs to allocate and use the DMA channel from user mode. I2S (i.e audio HAL) is the main user of these APIs. When the process that allocates the handles doesn't free-up and crashes, RM reftracker driver will clean up the handles its on-behalf. Same mechanism already exists for the mmeory handles. bug 730003 Change-Id: Iceb5c3b6d22989463d184c90e25ab06f6979b5a4 Reviewed-on: http://git-master.nvidia.com/r/7013 Tested-by: Victor (Weiguo) Pan <wpan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-20[ventana/rtc] enable rtc as wakeup event.Suresh Mangipudi
enable rtc as a valid wake up source/event on ventana. Bug 728544 (cherry picked from commit a93c1ee40eddaa6c2244c30f03868fb589fdf062) Change-Id: Ib1ee0211d3a69a6dbb83f6b78ebc89863c64a499 Reviewed-on: http://git-master.nvidia.com/r/6778 Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-19tegra-whistler-accelerometer: reverse x directiontegra-10.9.1Bharat Nihalani
X direction needs to be reversed to correct orientation in portrait mode for Whistler. Bug 678250 Reviewed-on: http://git-master/r/6661 Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> (cherry picked from commit 2406bc176b9bb86bd7b6c9e707c4e44b97d997d6) Change-Id: I35eff83ba9cb39d49062f2fb9e01d968543b7bde Reviewed-on: http://git-master/r/6767
2010-09-17[ARM/tegra] RM: Clean-up SPI hints/APB low corner.Alex Frid
- Completely removed busy hints for the SPI channel connected to PMU (busy hints were allowed for for CS, other than PMU, which may create dead-lock if channel access is serialized). - Increased APB low corner to 36MHz for reliable SPI communications at default low frequencies. Bug 721076 (cherry picked from commit 50ccc3cb8f0956370f1841e83133f47c88615889) Change-Id: I0a119610608bc5db4d7daea68bd9d4285d3715e8 Reviewed-on: http://git-master.nvidia.com/r/6744 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-16[ARM/tegra] RM: Wake Source InformationVictor(Weiguo) Pan
Print out wake status when resuming back from LP0. Bug 725727 Change-Id: Iede6aa7314e4912ff7ccadccbab90f097deab893 Reviewed-on: http://git-master.nvidia.com/r/6549 Tested-by: Victor (Weiguo) Pan <wpan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-16 [ARM/tegra] validate return code from sem_handle_insert callsAndy Carman
Bug 720137 (cherry picked from commit 3a86bacc8a8cf8c593028a7594867df00a45a189) Change-Id: I9a35a9a41c2d27e36ff651650633cf6c59cc2e57 Reviewed-on: http://git-master.nvidia.com/r/6456 Reviewed-by: Andy Carman <acarman@nvidia.com> Tested-by: Andy Carman <acarman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-16[arm/tegra] IPv6, UID_STAT configs supportRahul Bansal
To support IPv6 and Network Traffic Stats related CTS tests. Bug: 690020, 690023, 687255 Change-Id: I5b14c908ba544196da6000d598a11fd1b33780ef Reviewed-on: http://git-master/r/6597 Reviewed-by: Rahul Bansal <rbansal@nvidia.com> Tested-by: Rahul Bansal <rbansal@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-16[arm/tegra] dma and serial: Adding pointer checksLaxman Dewangan
Adding the valid pointer checks before accessing the pointers which is passed when public apis are called. Also resetting the pointers to null once the allocated handles are freed. (cherry picked from commit 0954407534a757b316bc35a0232968feed23243a) Change-Id: Ib8b99f0556fb9a98c74ba8911a00879451fad9e5 Reviewed-on: http://git-master/r/6578 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-15[ARM/tegra] RM: Updated HDMI PLLD settings.Alex Frid
Separated PLLD and PLLC HDMI settings. Changed PLLD settings to increase comparison frequency for 12MHz and 26MHz reference clocks. Kept PLLD settings for other reference clocks and all PLLC settings unchanged. Idempotent PLL configuration clean up. Bug 719667 Change-Id: I882ca2d8a98618518099a5b9482526d5556ba8ea Reviewed-on: http://git-master/r/6340 Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-14Merge remote branch 'origin/tegra-2010-09' into HEADMaria Gutowski
2010-09-13[arm/tegra] serial: Don't register uart channel if pinux is 0.Laxman Dewangan
If pinmux is not configured for the uart channel then will not be registering the uart device. bug 731336 (cherry picked from commit e496189740d18903db1de44cd96b96e07c93d8b7) Change-Id: Ib5a97425f991f16d280bfaabb00febacab392fe1 Reviewed-on: http://git-master/r/6373 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Harry Hong <hhong@nvidia.com> Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-13[ARM/tegra] ODM: Enabled EMC DFS for Samsung LPDDR2.Alex Frid
Enabled EMC DFS for Whistler E1112 board with Samsung LPDDR2. Bug 725563 Change-Id: I65cd32365f5739b1d82b1f0a84d794245a6c98a9 Reviewed-on: http://git-master/r/6319 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-09[ARM/tegra] RM: Set pulse mode for 3D busy hints.Alex Frid
Set pulse mode for 3D busy hints to speed up frequency/voltage decrease after hint is canceled. Bug 726052 (cherry picked from commit 58c01c2fc28a3e90e661954ab76cd7f65b0bd2cf) Change-Id: I77a77d9fc73b1675bdaddb08663cfed07900ffa7 Reviewed-on: http://git-master/r/6281 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-09[usb-msd]Fix to increase MSD write performanceVenkat Moganty
MSD write performance is decreased due to the file_sync() called in the write path this is introduced in the K32. After removing this write performance is increased and it is back to K29. Bug 727609 (cherry picked from commit 3674a60b8d4ede5d9305bf59a205e9f16e025f2a) Change-Id: I99e63302e1b189b600163c216847eae437e86a9f Reviewed-on: http://git-master/r/6246 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-06tegra accelerometer: Changed default initialization parametersPritesh Raithatha
Fixes bug 678250 Reviewed-on: http://git-master/r/5583 Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> (cherry picked from commit bcd2f2e113fb10b321272a53c2c0e015099e3ea8) Change-Id: I985af6334389e257ae6acd37e85c17391200b649 Reviewed-on: http://git-master.nvidia.com/r/6056 Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-06[arm/tegra]: Allocating dma action memory with zero init.Laxman Dewangan
In NvRmDmaStartDmaTransfer(), the memory is allocated for the dma action. The allocated memory does not get initialized and so uninitialized member unintentionally changing the behavior of dma. Allocating memory with zero initialized. bug 728661 (cherry picked from commit ac036af2c9599c419c12a8ba1c4309a9d8364b21) Change-Id: Ie36db6ad88eb9a9870f53b2c685eed6888decaf9 Reviewed-on: http://git-master.nvidia.com/r/6052 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-03[ARM/tegra] power: Added non-boot PLL restoration.tegra-10.8.3Alex Frid
Added non-boot PLL (PLLC/PLLA/PLLD) restoration during clock resume before clock dividers are restored. (Current restoration in RM happens late after clock dividers are restored). Change-Id: I9661f5ddba0ba4b25d5a00c78820792791777429 Reviewed-on: http://git-master/r/5515 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-09-03[arm/tegra] dma: Dma allocation should be thread safeLaxman Dewangan
The dma can be allocated from multiple client in run time and so it should be thread/smp safe. Returning proper error pointer in case of there is no dma to allocate. bug 723220 Change-Id: Ifb333d4b14e32be561e34a0d7668a2d631ac80c6 (cherry picked from commit db2d10f715fcdd6fdaf5fc7ea8e27a505f8332da) Reviewed-on: http://git-master/r/5769 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-03[arm/tegra] rm dma: Fixing resource leak issue.Laxman Dewangan
When dma is aborted, all request should be dequeued from the dma and the allocated memory should be freed. The allocated resource was not getting freed, fixing this issue. Properly checking the return pointer from the allocate_dma. (cherry picked from commit 02f0e4da9c66fee14f4492fa5b4ec41fd028a56e) Change-Id: I0dbaeca9b19331458b9aaf91556b7dad1e9b67ee Reviewed-on: http://git-master/r/5768 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-03[arm/tegra]spi:Restricting interface freq to less than requestedLaxman Dewangan
The maximum interface frequency configured by the spi driver should not more than the requested interface freq. Correcting the passed argument to behave the clock driver accordingly. Change-Id: I6e1beea7f01fb410f5e2755406b7d4dac7fd570d Reviewed-on: http://git-master/r/5573 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-09-01[tegra/arm] Use inner shareable I-cache BTB on SMPJon Mayo
merge of the following two patches: ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Change-Id: Ie98623b758f8d2d5dabc436ab536ed83efed59f4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/5826 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-31tegra vibrator: Fixing vibrator issues on froyo+K32Venu Byravarasu
1. Changing name field of tegra_vibrator to vibrator 2. Removing vibrator references from board-nvodm.c bug: 702248 Tested on: whistler Change-Id: Ie323e2ee74c4f89b0505f6e3aed1d87f57b388c8 Reviewed-on: http://git-master/r/5795 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-30[arm/tegra] spi: Configuring desired CS for slave communication.Laxman Dewangan
The desired chipselect id which is passed from the slave transaction api is not getting set and so it was not possible to do slave communication on different CS other than 0. Fixing this issue. Change-Id: I91d3b10b7ec01af98a4912ed05f9068491626ba9 Reviewed-on: http://git-master/r/5425 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-30[odm/pmu] tps6586: Fixing external rail control issue.Laxman Dewangan
The external power rail Ext_TPS74201PmuSupply_LDO is controlled by the gpio 1 of the tps6586. When gpio output is set to 0, the rail output is ON and when gpio output is set to 1, the rail output is OFF. As the api provides the control of these external rails through tps6586, the gpio output control should be on the desired value of external rails. Also by default power on, the external power rail Ext_TPS74201PmuSupply_LDO is ON so making it OFF as part of pmu setup. Change-Id: I05e2700afc719065f723b6f78b8cef829dcd4e53 Reviewed-on: http://git-master/r/5558 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-29[ventana/ulpi] ulpi low power stateSuresh Mangipudi
Release the ulpi gpio before entering lp0. Bug 718123 Change-Id: I6a07f6df723b7192a3b83dbda1cde39b4dd75b93 Reviewed-on: http://git-master/r/5088 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-27[arm/tegra]dma:Continuous double buffer repeat transfer.Laxman Dewangan
To get the higher performance on uart receive, it is required to have the transfer mode of continuous double buffer of dma operation on the client buffer. The dma keeps filling same buffer and informs client when half buffer and full buffer transfer completes. Also added support to start and stop without enqueing/dequeueing. Bug 725085 Change-Id: I994af55d5e5b2e7f17b889aaa00ca57942bebac8 Reviewed-on: http://git-master/r/4630 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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