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2012-03-09ENGR00170244-1 ARM: AHCI: Enable PDDQ mode when no disk is attachedRichard Zhu
In order to save the power consumption, enable the PDDQ mode of AHCI PHY when there is no sata disk on the port Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit a53c29d7e484a3562e3a4f24d952485fbeb4c933)
2012-03-09ENGR00170342 PWM: fix pwm output can't be set to 100% full dutyYuxi Sun
The chip document says the counter counts up to period_cycles + 1 and then is reset to 0, so the actual period of the PWM wave is period_cycles + 2 Signed-off-by: Yuxi Sun <b36102@freescale.com> (cherry picked from commit e1465447502c77b2951af7ace43d8f76fa5039fb)
2012-03-09ENGR00169603 MX53 ARD: FlexCAN: Set lp_apm as clock sourceRogerio Pimentel
The FlexCAN clock source must be lp_apm (24MHZ) instead ipg_clock_root (60MHZ) to meet automotive clock requirements. Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> (cherry picked from commit b7456a4f5f6fa12235effbffe4e4d1b62159b948)
2012-03-09ENGR00162578 DMA mx5: increase DMA Zone size to 112Robin Gong
Increase DMA zone size from 96 to 112 size, and default size is 112, change imx5_defconfig, change SPBA0_BASE_ADDR_VIRT from 0xFB100000 to 0xF7C00000 , so that it can't overlap with DMA zone Signed-off-by: Robin Gong <B38343@freescale.com> (cherry picked from commit 2d04dcb9b717a7c46358987f41a03141eccc42b0)
2012-03-09ENGR00163698 MX53 ARD: fix typo error for pwm1 pad disable functionYuxi Sun
Fix typo error for pwm1 pad disable function. Signed-off-by: Yuxi Sun <b36102@freescale.com> (cherry picked from commit d04b2646528b586baeecc1f128508b5363e7ed63)
2012-03-09ENGR00162708 MX5: Add I2C dummy write and mask nONKEY event for i2c operationWayne Zou
MX5: Add I2C dummy write when acessing DA9053 registers and mask nONKEY event for i2c operation before suspend Signed-off-by: Wayne Zou <b36644@freescale.com> (cherry picked from commit 0cc56da7dc91bbd5b6e9a51c1576daedce36093c)
2012-03-09ENGR00161215-1 arch/arm: Add two new IOCTLs in mxc_vpu.hSammy He
Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM for vpu driver. The two ioctls can be used when user allocates working buffer from user space, for exmaple, allocating it from pmem interface on android, then register it to vpu driver. Signed-off-by: Sammy He <r62914@freescale.com> (cherry picked from commit ad29cb1c2ad8ca4bbb30ff2ff55a4e8888b08373)
2012-03-09ENGR00155891 mx53_loco: enable mc34708's WDI function and pin configurationRobin Gong
Because of reboot failure, we add mc34708's WDI reset function and the pin's mux function when system reboot. So mc34708 will be reset when AP reboot. Signed-off-by: Robin Gong <B38343@freescale.com> (cherry picked from commit 8e03278824625e8d528e129ad49e094e4d533f87)
2012-03-09ENGR00157473 MX5X: UART: disable UART2 DMA to make GPS work.Zhang Jiejing
After enable DMA, GPS will keep report these DMA error: UART: DMA_ERROR: sr1:2010 sr2:508b UART: DMA_ERROR: sr1:2050 sr2:508a UART: DMA_ERROR: sr1:2050 sr2:508b UART: DMA_ERROR: sr1:10 sr2:1083 UART: DMA_ERROR: sr1:50 sr2:1082 UART: DMA_ERROR: sr1:2010 sr2:508b UART: DMA_ERROR: sr1:2050 sr2:508a UART: DMA_ERROR: sr1:2010 sr2:508b UART: DMA_ERROR: sr1:2010 sr2:508b UART: DMA_ERROR: sr1:2010 sr2:508b UART: DMA_ERROR: sr1:50 sr2:1083 Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com> (cherry picked from commit ddaf091fd3f5fae56b3c83f5cf59ee4f189f0a40)
2011-09-14ENGR00156183-1 mx53_loco: add get_pins/put_pins call back for sii902xJason Chen
there is hardware pin conflict between sii902x DET and egalax touch screen on mx53 loco board. Request gpio during sii902x probe can fix this conflict only when these two module not co-exist. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-09-06ENGR00155137 mx53 Ripley: enable SWBST in stop modeRobin Gong
Because VUSB is supply by SWBST , we shouldn't off SWBST, otherwise VUSB will not kept in 3.3V , so there is no normal wakeup signal produced when USB device plug in or out after system go into stop mode. Signed-off-by: Robin Gong <B38343@freescale.com>
2011-09-01ENGR00155638 mx53 power: Add DDR float pin operation when system idleWayne Zou
1. Add DDR self-refresh mode and float pin operation when system idle For audio playback use case on android r10.3, it can save 10mA@1.54V about 15mW on DDRIO+ memory power, and 6.6mA@2.5V -16.5mW on VDD_REG It can reduce more memory power consumption if cpu idle time is longer 2. remove the L1/L2 cache operation during suspend for mx53 The L1/L2 cache are powered by VDDA/VDDAL1 and they should be supplied according to iMX53 datasheet, there is also no EMPG on MX53, so it can be removed to improve system performance and power. 3. remap the suspend_iram_base as MT_MEMORY_NONCACHED instead of MT_HIGH_VECTORS If the IRAM page is marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to DDR, so it can fill those lines with IRAM instruction code. The problem is that the DDR is in self-refresh mode and HighZ DDR IO PADs during system idle or suspend, so any DDR access causes the ARM MPU subsystem to hang. It needs to cherry-pick two patches(5a4aeb9f6,7c8d972d8) from community. 4. Add DDR self-refresh mode and float pin operation for mx53 ARD board, and mx53 QS/Ripley board This patch can resovle ramdom suspend/resume issue, since the early code didn't consider the TLB missing case during suspend. It needs to save all the M4IF/IO MUX registers firstly to make sure the page table entried into TLB, and then enter DDR self-refresh mode. Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-08-31ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flagsSantosh Shilimkar
The commit f1a2481c0 sets up the default flags for MT_MEMORY and MT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly set as default for these entries so remove it. Also adding the 'L_PTE_WRITE' flag so that these pages become read-write instead of just being read-only [this stops them being exposed to userspace, which is the main concern here --rmk] Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-31ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entriesSantosh Shilimkar
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary additional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-30Do not call flush_cache_user_range with mmap_sem heldDima Zavin
[ARM] Do not call flush_cache_user_range with mmap_sem held We can't be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock. Also, since we really can't be holding the mmap_sem while calling flush_cache_user_range AND vma is actually unused by the flush itself, get rid of vma as an argument. Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106 Signed-off-by: Dima Zavin <dima@android.com>
2011-08-29ENGR00155472 mx53_loco: support for RevB and RevA of Ripely mx53_locoRobin Gong
in board_init ,kernel will read the system_rev TAG from uboot and configure the right interrupt gpio Signed-off-by: Robin Gong <B38343@freescale.com>
2011-08-24ENGR00144145-1 usb: can be built as loadable modulesPeter Chen
MSL part Follow below load sequence to use OTG - fsl_otg_arc - ehci-hcd - arcotg_udc Besides, in order to match i.mx53 release windows, it changes some common code, there will be a better solution at 2.6.38 in future Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-08-22ENGR00155173 mx53_ard: fix CAN unable to communicate issueDong Aisheng
Merge this patch for SR 1-775080061. The error is the system can find the CAN bus, but cannot communicate physically. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2011-08-22ENGR00155100 mx5: Use CONFIG_MXS_DMA_ENGINE to control DMA codeLily Zhang
Use CONFIG_MXS_DMA_ENGINE flag to control mxs dma engine code Signed-off-by: Lily Zhang <r58066@freescale.com>
2011-08-22ENGR00154458 Mx53 clock: close ssi_ext1_clkYuxi Sun
Set this clock closed by default, and open it when it is needed. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2011-08-19ENGR00144056 MX53_SMD: COIN_CELL, no power supply for coin cellWayne Zou
enable coin cell battery charger Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-08-05ENGR00154300-1 SDMA: Fix Mx53 ASRC not works with SSIZeng Zhaoming
The following case not works in mx53: memory --> asrc --> ssi It is partly caused by asrc --> ssi using per_2_per sdma script to transfer data. And this script not works in sdma driver. In the per_2_per script, two sdma events trigger one channel, the watermark level setting different from ordinary sdma script, we need to set two watermark levels and map each watermark to event one-by-one. Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
2011-08-04ENGR00144281 SDMA: System hangs in bootup when kernel_preempt not enableZeng Zhaoming
When kernel_preempt not enable in configure, system bootup hangs in sdma initialization. This is caused by sdma initialization waiting for channel0 complete loading script in queue, and arch_idle happens with action to disable some clocks, if DDR clock disabled, script loading will failed and SoC hangs. Solve it by make sure DDR clock is enabled during sdma initialization. Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
2011-07-30ENGR00153830-1 vpu: Add new VPU_IOC_REQ_VSHARE_MEM ioctl in mxc_vpu.hSammy He
Add new VPU_IOC_REQ_VSHARE_MEM ioctl to request vmalloced share memory. Signed-off-by: Sammy He <r62914@freescale.com>
2011-07-27ENGR00153728: Fix MX25, MX31 build break caused by ENGR00153576Ranjani Vaidyanathan
Fix build break for non-mx5x platforms Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-07-27ENGR00153741 MX5 PM: fix a NULL pointer reference when enter suspendWayne Zou
Fix the NULL pointer reference when there is no struct mxc_pm_platform_data defines on MX5 machines. Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-07-26ENGR00153586 mx53 ard: add mma8451 supportLily Zhang
Add mma8451 support for mx53 ard board. Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Angolini Daiane <B19406@freescale.com>
2011-07-25ENGR00153567: MX5x - Fix race condition in clock codeRanjani Vaidyanathan
There is possible race condition between enabling/disabling clocks and the corresponding calls to change the bus frequencies. Fix by ensuring that the flags used to change the bus frequencies are set in a atomic context and before the bus frequency is actually changed. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-07-22ENGR00153424-2 turn on ddr clock for audio buffers in external ramAlan Tull
Audio is broken if buffers are in external ram and the external ram clock is turned off. To fix it: * In platform data, ext_ram is replaced with two settings: ext_ram_rx and ext_ram_tx which control whether the buffer will be in iram or external ram. * imx-pcm.c no longer hardwired to put all capture streams in external ram. * if IRAM is disabled in the defconfig or if iram_alloc fails, then ext_ram_rx or ext_ram_tx are updated so they will show whether the buffers were allocated in external ram or iram. * During audio playback or capture, enable external ram clock if the buffer is in external ram. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-07-22ENGR00153275-2 mx53 L2635 msl modifications when add ahci temp-monitorRichard Zhu
based on the 2.6.35 kernel mainline, refer to linux std hwmon architeture, add the standalone ahci temperature monitor driver on fsl i.mx53 platforms. Signed-off-by: Richard Zhu <r65037@freescale.com>
2011-07-21ENGR00151310 mx53 smd: remove GPIO_9 pull downLily Zhang
This patch is used to remove the workaround "pull down GPIO_9" to support reboot in mx53 SMD. Another workaround is adopted into U-Boot to force warm reset as cold reset. New workaround can support watchdog timeout in mx53 SMD board. Signed-off-by: Lily Zhang <r58066@freescale.com>
2011-07-21ENGR00153378 MX53 cleanup pm suspend/resume source code V2Wayne Zou
restructure the pm suspend/resume routines as mxc_pm_platform_data, so split the SOC pm routines from machine pm routines. Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-07-19ENGR00153298 MX53_SMD: set camera reset pin as outputYuxi Sun
This pin was not set before, it seems default as input, so need to set as output Signed-off-by: Tu Chih Chieh <b32449@freescale.com>
2011-07-18ENGR00153261: MX50- Disable Auto clock gating of APLL.Ranjani Vaidyanathan
The HW automatically tries to clock gate APLL is all the PFDs are disabled, resulting in a possible race condition since the SW also tries to disable the APLL. Fix by clearing the PFD disable MASK bits in APLL. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-07-15ENGR00153158: MX51-Increase AHB_CLK to 66.5MHz if SDHC is activeRanjani Vaidyanathan
Random failures can occur if SDHC clk is below AHB_CLK. So ensure that ahb_clk is atleast 66.5MHz when SDHC is active. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-07-14ENGR00153157: MX51- Fix random failure when exiting LPAPM mode.Ranjani Vaidyanathan
The system randomly hangs when exiting LPAPM mode on MX51. The root cause of the issue because the parent of periph_apm_clk cannot be changed when main_bus_clk is sourced from it. To fix the issue, we cannot use periph_apm_clk to source main_bus_clk in LPAPM mode. Instead we need to divide down PLL2 using dvfs_podf and use individual dividers to further reduce other clocks in PLL2 domain. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-07-13ENGR00152557 Add fuse bit check for GPU/VPUTerry Lv
Add fuse bit check for GPU/VPU. Some boards may not have GPU/VPU. This can be controlled by fuse bit. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-07-01ENGR00152359-1 sii902x hdmi: add AVI and AIF support.Jason Chen
1.add AVI and AIF support. 2.add edid 4-block reading support.(not test) Signed-off-by: Jason Chen <b02280@freescale.com>
2011-06-30ENGR00151885: MX50 - Add SW workaround fro DPLL unlock HW issue.Ranjani Vaidyanathan
Add the workaround that significantly reduces the occurrence of the PLL1 unlock HW issue. For MX50, this workaround needs to be applied in three places: 1. Suspend/resume code. 2. PLL1 set rate function. 3. PLL1 enable Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-06-23ENGR00151334 MX5X: disable dvfs_core when system poweroff.Zhang Jiejing
This Patch is fix for the reboot bug, our mx51,mx53 will hang after reboot more then 20 times(100%). We found this bug is caused by enable dvfs, so this patch disable dvfs when system poweroff. kernel panic log is like: Kernel panic: (attached full logs) MXC Watchdog # 0 shutdown Restarting system. Unable to handle kernel paging request at virtual address fffffffc pgd = 99e54000 [fffffffc] *pgd=90ce6021, *pte=00000000, *ppte=00000000 Internal error: Oops: 817 [#1] PREEMPT last sysfs file: /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state Modules linked in: CPU: 0 Not tainted (2.6.35.3-01072-gb754390 #1) PC is at 0x99ce02bc LR is at 0x84de7d4b pc : [<99ce02bc>] lr : [<84de7d4b>] psr: 20000013 sp : 99ce1e68 ip : 00004076 fp : 00000000 r10: f9ffffff r9 : 00000068 r8 : 8003a104 r7 : 00000000 r6 : 0000203c r5 : 28121969 r4 : 00000000 r3 : ec860ad4 r2 : 00000000 r1 : 00000000 r0 : fffffffc Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c5387d Table: a9e54019 DAC: 00000015 Process reboot (pid: 2484, stack limit = 0x99ce02e8) Stack: (0x99ce1e68 to 0x99ce2000) 1e60: 00000000 00000000 80042690 8003aff0 00000000 28121969 1e80: 01234567 8003aa54 00000000 8007a438 00000000 99ce1ed4 980029d0 99ce1ed4 1ea0: 000508fb 99ce1f14 99ce0000 800ee880 00000000 800a6fc8 99ce1edc 980029d0 1ec0: 00000000 8009f6b8 0000000e 99ce1ef8 980029d0 00000000 00000000 99ce1f94 1ee0: 99ce0000 800ee880 00000000 800a5a9c 99ce1ef8 8009f7ec 00000001 00000000 1f00: 00000000 7fffffff 00000000 00000000 00000000 00000000 ffffffff 508fb800 1f20: 00000000 508fb7ff 00000000 99ce1f94 99ce0000 800ee880 00000000 8009f784 1f40: 508fb7ff 00000000 99ce1e8c 00000000 980029d0 99a21640 808c4d0c 800a00a0 1f60: 99a21800 99ce0000 99a21800 800ce5b4 0001b6dc 7e90caf4 00000001 00000024 1f80: 8003a104 99ce0000 00000000 800ee7ac 00000001 0001b6dc 7e90caf4 00000001 1fa0: 00000058 80039f80 0001b6dc 7e90caf4 fee1dead 28121969 01234567 00000000 1fc0: 0001b6dc 7e90caf4 00000001 00000058 00017047 00000000 00000000 00000000 1fe0: 0001b804 7e90ca88 6fd17763 6fd0c3ec 60000010 fee1dead 00000000 00000000 Code: 00000000 40000000 00000000 80039e90 (f4000000) ---[ end trace 7f263b4201ae9f59 ]--- Kernel panic - not syncing: Fatal exception [<8003e578>] (unwind_backtrace+0x0/0xf0) from [<8046e83c>] (panic+0x6c/0xe0) [<8046e83c>] (panic+0x6c/0xe0) from [<8003d420>] (die+0x2b4/0x304) [<8003d420>] (die+0x2b4/0x304) from [<8003f3e8>] (__do_kernel_fault+0x64/0x84) [<8003f3e8>] (__do_kernel_fault+0x64/0x84) from [<8003f5c8>] (do_page_fault+0x1c0/0x1d4) [<8003f5c8>] (do_page_fault+0x1c0/0x1d4) from [<800392c8>] (do_DataAbort+0x34/0x94) [<800392c8>] (do_DataAbort+0x34/0x94) from [<80039a2c>] (__dabt_svc+0x4c/0x60) Exception stack(0x99ce1e20 to 0x99ce1e68) 1e20: fffffffc 00000000 00000000 ec860ad4 00000000 28121969 0000203c 00000000 1e40: 8003a104 00000068 f9ffffff 00000000 00004076 99ce1e68 84de7d4b 99ce02bc 1e60: 20000013 ffffffff [<80039a2c>] (__dabt_svc+0x4c/0x60) from [<99ce02bc>] (0x99ce02bc) Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2011-06-22ENGR00151963: MX51 - Add SW workaround for DPLL unlock issue.Ranjani Vaidyanathan
The patch based on the following consumption: - PLL1 is already enabled when Linux boot up, this is true. - PLL1 is working on 800Mhz on MX51 - PLL1 does not change during system up, keep 800Mhz The patch will have the following side-effect - suspend/resume will take more time Before enter stop (WFI) mode (1) switch DDR and ARM to PLL2 (2) Disable AREN bit to avoid PLL1 restart during MFN change) (3) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179 thus the equation |MFN/(MFD+1)| < 1 (4) Manual restart PLL1 (5) Wait PLL1 lock After CPU out of WFI (6) Set PLL1 to 800Mhz with only change MFN to 60, others keep (7) Wait MFN change complete by delay more than 4.6us, (8) Switch DDR and ARM back to PLL1 Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-06-22ENGR00151891: MX50-Fix bug in exit from LPAPM mode.Ranjani Vaidyanathan
When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for a few instructions while the voltage is still at 0.85V. Fix this issue by setting the ARM-PODF divider before switching the parent. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-06-22ENGR00151900 vpu: fix build failure for mx3 platformSammy He
Fix build failure for mx3 platform due to ENGR00151494 push. Signed-off-by: Sammy He <r62914@freescale.com>
2011-06-21ENGR00151494-2 arch: change mxc_vpu.h to remove definition for mx32/mx37Sammy He
The vpu code in driver for mx32/mx37 is out of date already, and we won't support the platforms, so clean the code for removing it. And removed ioctl definition that won't use again. Signed-off-by: Sammy He <r62914@freescale.com>
2011-06-20ENGR00151762 vpu: Fix system hang due to long time video playback on mx51Sammy He
Fix system hang due to long time video playback. This issue is only on i.MX51 platfrom due to changing vpu clock parent in vpu_enable/ disable. Set vpu clock parent to axi_a forever to fix it. Signed-off-by: Sammy He <r62914@freescale.com>
2011-06-17ENGR00151697 MX51 BBG:Correct backlight iomuxLiu Ying
Blank DI0 framebuffer will switch off the backlight of WVGA LCD panel on DI1. This patch corrects the iomux of backlight controlling pin, which is configured to a gpio pin. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2011-06-14ENGR00151476-1 mx5: remove build warning messageLily Zhang
Remove build warning message for mx5 platform Signed-off-by: Lily Zhang <r58066@freescale.com>
2011-06-13ENGR00144479 MX53_SMD Suspend/Resume: Auto resume from stop mode at first timeWayne Zou
The GPIO9 on da9053 chip is floating on board, and it is configured as input before suspend. Fixed it by mask the interrupt source on da9053. Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-06-10ENGR00151370 ahci: re-add the temperature monitor sysfsRichard Zhu
Add the AHCI temperature monitor sysfs API that removed accidently in ENGR00144104 Signed-off-by: Richard Zhu <r65037@freescale.com>
2011-06-03ENGR00144428 mx51BBG: fix segment fault when suspend for no da9053Wayne Zou
mx51BBG: fix segment fault when suspend for no da9053 present Signed-off-by: Wayne Zou <b36644@freescale.com>
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