linux-toradex.git - Linux kernel for Apalis, Colibri and Verdin modules

Age	Commit message (Expand)	Author
2015-09-21	clk: pistachio: correct critical clock list	Damien.Horsley
2015-09-21	clk: pistachio: Fix PLL rate calculation in integer mode	Zdenko Pulitika
2015-09-21	clk: pistachio: Fix override of clk-pll settings from boot loader	Zdenko Pulitika
2015-09-21	clk: pistachio: Fix 32bit integer overflows	Zdenko Pulitika
2015-06-04	clk: pistachio: Add sanity checks on PLL configuration	Kevin Cernekee
2015-06-04	clk: pistachio: Lock the PLL when enabled upon rate change	Ezequiel Garcia
2015-06-04	clk: pistachio: Add a pll_lock() helper for clarity	Ezequiel Garcia
2015-03-31	CLK: Pistachio: Register external clock gates	Andrew Bresticker
2015-03-31	CLK: Pistachio: Register system interface gate clocks	Andrew Bresticker
2015-03-31	CLK: Pistachio: Register peripheral clocks	Andrew Bresticker
2015-03-31	CLK: Pistachio: Register core clocks	Andrew Bresticker
2015-03-31	CLK: Pistachio: Add PLL driver	Andrew Bresticker
2015-03-31	CLK: Add basic infrastructure for Pistachio clocks	Andrew Bresticker