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path: root/drivers/clk
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2020-02-09ARM: imx7d: clk: add root clock for keypad portStefan Agner
The keypad port (KPP) module is clocked by the IPG root clock through clock gate CCM_CCGR170. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 7b51b6365ebcf65b1054337a5bb0e1879397aae6) (cherry picked from commit 09c36fb13aa73bac59709c5805f5f9f9e45acee9) Conflicts: include/dt-bindings/clock/imx7d-clock.h Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-02-09Revert "MLK-18724-3 clk: imx7d: remove IMX7D_NAND_USDHC_BUS_ROOT_CLK out ↵Marcel Ziswiler
from clks_init_on[]" This reverts commit 04b647fe39e7b1f2ccbcde2e9eccc596b5f2b9da. This fixes eMMC on sdhci3 being defunct just erroring out with -110. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-02-09Revert "MLK-14498-2 ARM: imx7d: clk: select uart clock parent and rate"Stefan Agner
This seems to limit possible baud rates due to lower input clock. Since Toradex modules do not use UART5/6 as console, do not set clock explicitly. This reverts commit 4f447cb8bccb1d40973e46478d7b11aa61961c90. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2020-02-09Revert "MLK-15120 ARM: imx7d: clk: select uart3 clock parent and set rate"Stefan Agner
This seems to limit possible baud rates due to lower input clock. Since Toradex modules do not use UART3 as console, do not set clock explicitly. This reverts commit 89869792e2f59c81354f9a53280c4eb6e95f4a9a. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2020-02-09ARM: imx7d: clk: make sure OCOTP clock is always onStefan Agner
Some device make use of the OCOTP via syscon. While the OCOTP node specifies a clock, in newer kernels the access via syscon does not enable the clock! During the main boot phase this is not usually a problem since the clock is initially on. However, after unused clocks get disabled, any access leads to a freeze. This has been observed when the i.MX Thermal driver probe has been deferred: The driver tried to read the calibration data from OCOTP via syscon and caused a system freeze. In upstream Linux this has recently been resolved using the NVMEM framework, see: Commit ae6215576d6b ("thermal: imx: Add support for reading OCOTP through nvmem") Commit a6c856e9a8cd ("ARM: dts: imx6sx: Use nvmem-cells for tempmon") Use a simpler work around by just adding the clock to the list of clocks which should kept on. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2020-02-09ARM: imx: clk: enable OCOTP clock by defaultStefan Agner
For some reason USDHC and USB access crashes the kernel if the OCOTP clock is not enabled. It seems not to be software related since there is no direct access from the USDHC/Chipidea USB driver to the OCOTP IP. It might be that the hardware checks the fuses to determine if the particular SoC is supposed to let user access a certain peripheral... Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit bce5146373372651052654b84cd3b773ac4d1882)
2020-02-09ARM: imx: clk: do not force clock frequency of M4Stefan Agner
Let the M4 handle the clock frequency by itself. We also don't need to take care to make sure clocks stay on, the per domain CCM clock gate control registers can be used to let the CCM know that the M4 runs on that PLL: CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun); Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 98adbbaef78b8a401350a0bf27c3ddc1881ec34d)
2020-02-09clk-imx6q.c: set eth phy clock dependent on RMII/RGMIIMax Krummenacher
Evaluate the device tree to find out about the used phy mode rather than using a hardcoded value of 125MHz valid for RGMII only. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 97f5120f2330550d500231b7bf27e7433fd31508) (cherry picked from commit 691204a1e59f6427688adba36797478c44c1dcca)
2020-02-09ARM: imx7d: clk: add 240MHz sys main clock to init_onStefan Agner
Add the 240MHz sys main clock to the init on list to make sure it is kept enabled by Linux. This allows to enable/debug the M4 core after Linux started. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit bef7a90406b663a74aaaf06bdccc56285d9fe93c) (cherry picked from commit 4af562c1388ee6edfd9579f4c34e2541cf92d69a)
2020-02-09ARM: imx: fix clock for i.MX 7 when Cortex-M4 is runningStefan Agner
Commit b0149f1c7c ("MLK-11620 ARM: imx: single SOC config/compile support") ifdef'd clock functionality for SoloX only if Cortex-M4 is running. However, i.MX 7 also provides a Cortex-M4, hence the true branch in those if statements have been taken. Since the whole block was ifdef'd, the functions were rendered useless for i.MX 7. Fix this by just doing the same thing as if Cortex-M4 is not running. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 7b20ca6cdb752ac4770c2c11e9500b7c1d8bc395) (cherry picked from commit bcdfec99c4d8aee54a5bc1ea706f0fcf4f48523d)
2020-02-07Merge tag 'v4.14.164' into 4.14-2.3.x-imxMarcel Ziswiler
This is the 4.14.164 stable release Conflicts: arch/arm/Kconfig.debug arch/arm/boot/dts/imx7s.dtsi arch/arm/mach-imx/cpuidle-imx6q.c arch/arm/mach-imx/cpuidle-imx6sx.c arch/arm64/kernel/cpu_errata.c arch/arm64/kvm/hyp/tlb.c drivers/crypto/caam/caamalg.c drivers/crypto/mxs-dcp.c drivers/dma/imx-sdma.c drivers/gpio/gpio-vf610.c drivers/gpu/drm/bridge/adv7511/adv7511_drv.c drivers/input/keyboard/imx_keypad.c drivers/input/keyboard/snvs_pwrkey.c drivers/mmc/core/block.c drivers/mmc/core/queue.h drivers/mmc/host/sdhci-esdhc-imx.c drivers/net/can/flexcan.c drivers/net/can/rx-offload.c drivers/net/ethernet/freescale/fec_main.c drivers/net/wireless/ath/ath10k/pci.c drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c drivers/pci/dwc/pci-imx6.c drivers/spi/spi-fsl-lpspi.c drivers/usb/dwc3/gadget.c include/net/tcp.h sound/soc/fsl/Kconfig sound/soc/fsl/fsl_esai.c
2020-01-04clk: pxa: fix one of the pxa RTC clocksRobert Jarzmik
[ Upstream commit 46acbcb4849b2ca2e6e975e7c8130c1d61c8fd0c ] The pxa27x platforms have a single IP with 2 drivers, sa1100-rtc and rtc-pxa drivers. A previous patch fixed the sa1100-rtc case, but the pxa-rtc wasn't fixed. This patch completes the previous one. Fixes: 8b6d10345e16 ("clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Link: https://lkml.kernel.org/r/20191026194420.11918-1-robert.jarzmik@free.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-01-04clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo
[ Upstream commit efd164b5520afd6fb2883b68e0d408a7de29c491 ] Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just some constant ratio from the input across the entire frequency range. It would be great if we could specify the frequency table as a single entry constant ratio instead of a long list, ie: { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, { } So, lets support that. We need to fix a corner case in qcom_find_freq() where if the freq table is non-null, but has no frequencies, we end up returning an "entry" before the table array, which is bad. Then, we need ignore the freq from the table, and instead base everything on the requested freq. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven
[ Upstream commit 515b2915ee08060ad4f6a3b3de38c5c2c5258e8b ] According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock of the DU module clocks on R-Car D3 is S1D1. Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai
[ Upstream commit 7bb7d29cffdd24bf419516d14b6768591e74069e ] The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0. Fix it. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: rockchip: fix I2S1 clock gate register for rk3328Katsuhiro Suzuki
[ Upstream commit 5c73ac2f8b70834a603eb2d92eb0bb464634420b ] This patch fixes definition of I2S1 clock gate register for rk3328. Current setting is not related I2S clocks. - bit6 of CRU_CLKGATE_CON0 means clk_ddrmon_en - bit6 of CRU_CLKGATE_CON1 means clk_i2s1_en Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: rockchip: fix rk3188 sclk_mac_lbtest parameter orderingHeiko Stuebner
[ Upstream commit ac8cb53829a6ba119082e067f5bc8fab3611ce6a ] Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc gate data") there is one other gate clock in the rk3188 clock driver with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: rockchip: fix rk3188 sclk_smc gate dataFinley Xiao
[ Upstream commit a9f0c0e563717b9f63b3bb1c4a7c2df436a206d9 ] Fix sclk_smc gate data. Change variable order, flags come before the register address. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Johan Jonker <jbx9999@hotmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17clk: sunxi-ng: a64: Fix gate bit of DSI DPHYJagan Teki
[ Upstream commit ee678706e46d0d185c27cc214ad97828e0643159 ] DSI DPHY gate bit on MIPI DSI clock register is bit 15 not bit 30. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-05clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()Alexandre Belloni
commit c1e4580a1d0ff510d56268c1fc7fcfeec366fe70 upstream. Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it easier to do it from code that is not parsing device tree. Also, this fixes an issue where the resulting clk_hw can be dereferenced before being tested for error. Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-12-05clk: at91: fix update bit maps on CFG_MOR writeEugen Hristev
commit 263eaf8f172d9f44e15d6aca85fe40ec18d2c477 upstream. The regmap update bits call was not selecting the proper mask, considering the bits which was updating. Update the mask from call to also include OSCBYPASS. Removed MOSCEN which was not updated. Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-12-05clk: ti: dra7-atl-clock: Remove ti_clk_add_alias callPeter Ujfalusi
[ Upstream commit 9982b0f69b49931b652d35f86f519be2ccfc7027 ] ti_clk_register() calls it already so the driver should not create duplicated alias. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lkml.kernel.org/r/20191002083436.10194-1-peter.ujfalusi@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-05clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18Colin Ian King
[ Upstream commit cdfc2e2086bf9c465f44e2db25561373b084a113 ] The zero'ing of bits 16 and 18 is incorrect. Currently the code is masking with the bitwise-and of BIT(16) & BIT(18) which is 0, so the updated value for val is always zero. Fix this by bitwise and-ing value with the correct mask that will zero bits 16 and 18. Addresses-Coverity: (" Suspicious &= or |= constant expression") Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-05clk: at91: avoid sleeping earlyAlexandre Belloni
[ Upstream commit 658fd65cf0b0d511de1718e48d9a28844c385ae0 ] It is not allowed to sleep to early in the boot process and this may lead to kernel issues if the bootloader didn't prepare the slow clock and main clock. This results in the following error and dump stack on the AriettaG25: bad: scheduling from the idle thread! Ensure it is possible to sleep, else simply have a delay. Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20190920153906.20887-1-alexandre.belloni@bootlin.com Fixes: 80eded6ce8bb ("clk: at91: add slow clks driver") Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-05clk: samsung: exynos5420: Preserve PLL configuration during suspend/resumeMarek Szyprowski
[ Upstream commit e9323b664ce29547d996195e8a6129a351c39108 ] Properly save and restore all top PLL related configuration registers during suspend/resume cycle. So far driver only handled EPLL and RPLL clocks, all other were reset to default values after suspend/resume cycle. This caused for example lower G3D (MALI Panfrost) performance after system resume, even if performance governor has been selected. Reported-by: Reported-by: Marian Mihailescu <mihailescu2m@gmail.com> Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-05clk: meson: gxbb: let sar_adc_clk_div set the parent clock rateMartin Blumenstingl
[ Upstream commit 44b09b11b813b8550e6b976ea51593bc23bba8d1 ] The meson-saradc driver manually sets the input clock for sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB, GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up to sar_adc_clk_sel which will let the common clock framework select the best matching parent clock if we want that. This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk drivers, which both also specify CLK_SET_RATE_PARENT. Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-01clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clockIcenowy Zheng
[ Upstream commit 859783d1390035e29ba850963bded2b4ffdf43b5 ] In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner , the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-01clk: at91: audio-pll: fix audio pmc typeAlexandre Belloni
[ Upstream commit 7fa75007b7d7421aea59ff2b12ab1bd65a5abfa6 ] The allocation for the audio pmc is using the size of struct clk_audio_pad instead of struct clk_audio_pmc. This works fine because the former is larger than the latter but it is safer to be correct. Fixes: ("0865805d82d4 clk: at91: add audio pll clock drivers") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-01clk: mmp2: fix the clock id for sdh2_clk and sdh3_clkLubomir Rintel
[ Upstream commit 4917fb90eec7c26dac1497ada3bd4a325f670fcc ] A typo that makes it impossible to get the correct clocks for MMP2_CLK_SDH2 and MMP2_CLK_SDH3. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-11-24clk: samsung: Use clk_hw API for calling clk framework from clk notifiersMarek Szyprowski
[ Upstream commit 1da220e3a5d22fccda0bc8542997abc1d1741268 ] clk_notifier_register() documentation states, that the provided notifier callbacks associated with the notifier must not re-enter into the clk framework by calling any top-level clk APIs. Fix this by replacing clk_get_rate() calls with clk_hw_get_rate(), which is safe in this context. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-11-24clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420Joonyoung Shim
[ Upstream commit d32dd2a1a0f80edad158c9a1ba5f47650d9504a0 ] The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to handle the bit only on exynos5420. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> [m.szyprow: rewrote commit subject] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-11-24clk: keystone: Enable TISCI clocks if K3_ARCHNishanth Menon
[ Upstream commit 2f149e6e14bcb5e581e49307b54aafcd6f74a74f ] K3_ARCH uses TISCI for clocks as well. Enable the same for the driver support. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-11-21MLK-22998-2 clk:imx8qm Update SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit 6dcd0242ae Removed unused clocks Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-11-20MLK-23006 clks:imx8qx: Fix dc_axi_int_clk to 375MhzRanjani Vaidyanathan
ECO fix done in QXP C0 for errata 'ERR050060: DC: PRG on the fly bypass switch issue' mandates that the axi_internal_clk frequency be limited to 375MHz. Per designer and verification team there is no performance drop in B0 due to this lower frequency. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-11-08MLK-22934-2: clk: imx8qxp: Remove unused audio clockShengjiu Wang
Remove below audio clocks from clk tree. IMX8QXP_ACM_AUD_CLK0_CLK IMX8QXP_ACM_AUD_CLK1_CLK, IMX8QXP_ACM_ASRC0_MUX_CLK_SEL IMX8QXP_ACM_ASRC0_MUX_CLK_CLK IMX8QXP_ACM_ASRC1_MUX_CLK_CLK IMX8QXP_ACM_ASRC1_MUX_CLK_SEL There are no these clocks physically. which are added wrongly before, so remove them. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-08MLK-22934-1: clk: imx8qm: Remove unused audio clockShengjiu Wang
Remove below audio clocks from clk tree. IMX8QM_ACM_AUD_CLK0_CLK IMX8QM_ACM_AUD_CLK1_CLK, IMX8QM_ACM_ASRC1_MUX_CLK_CLK IMX8QM_ACM_ASRC1_MUX_CLK_SEL There are no these clocks physically. which are added wrongly before, so remove them. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
2019-11-06clk: boston: unregister clks on failure in clk_boston_setup()Yi Wang
[ Upstream commit 8b627f616ed63dcaf922369fc14a5daf8ad03038 ] The registered clks should unregister when something wrong happens before going out in function clk_boston_setup(). Signed-off-by: Yi Wang <wang.yi59@zte.com.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-11-01MLK-22879-01 clk: imx: Add no cached flag for dram pllJacky Bai
When doing DRAM frequency change, the DRAM PLL config will be changed in ATF side, so add 'CLK_GET_RATE_NOCACHE' flag to make sure each time we get the DRAM PLL frequency through 'clk_get_rate' API, we can get the correct frequency. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2019-10-21MLK-21690 clk: imx8qm/imx8qxp: Store clock rate in SCU clock driverRanjani Vaidyanathan
Linux clock framework does not work correctly when the SCFW API returns the rate of the clock based on the HW power mode (LP vs ON). This causes issues in two ways: 1. Linux clock framework always calls clk_recalc() after set_rate() as a mechanism to get the actual rate set by the HW. This does not work on iMX8QM/iMX8QXP when the resource is in LP mode, as clocks are sourced from 24MHz when resource is in LP mode. 2. On iMX8QM/iMX8QXP multiple resources share the same power domain. As resources enter runtime idle, the iMXQM/QXP power domain driver in Linux sets the resources in LP mode which can result in the entire power domain entering LP mode. If a clock get_rate()/recalc_rate() is executed as part of probing a new driver, the rate returned by SCFW API will not match the rate requested by the driver. To fix the above two problems, store the clock rate in SCU driver and return the stored clock rate if the resource is in LP mode. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> (cherry picked from commit 7868227a9b7b27b808e43544f1a367fc3eebde50)
2019-10-07clk: at91: select parent if main oscillator or bypass is enabledEugen Hristev
[ Upstream commit 69a6bcde7fd3fe6f3268ce26f31d9d9378384c98 ] Selecting the right parent for the main clock is done using only main oscillator enabled bit. In case we have this oscillator bypassed by an external signal (no driving on the XOUT line), we still use external clock, but with BYPASS bit set. So, in this case we must select the same parent as before. Create a macro that will select the right parent considering both bits from the MOR register. Use this macro when looking for the right parent. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-10-07clk: zx296718: Don't reference clk_init_data after registrationStephen Boyd
[ Upstream commit 1a4549c150e27dbc3aea762e879a88209df6d1a5 ] A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815160020.183334-3-sboyd@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-10-07clk: sirf: Don't reference clk_init_data after registrationStephen Boyd
[ Upstream commit af55dadfbce35b4f4c6247244ce3e44b2e242b84 ] A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Guo Zeng <Guo.Zeng@csr.com> Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-6-sboyd@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-10-07clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocksIcenowy Zheng
[ Upstream commit 720099603d1f62e37b789366d7e89824b009ca28 ] The MMC2 clock slices are currently not defined in V3s CCU driver, which makes MMC2 not working. Fix this issue. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-10-07clk: qoriq: Fix -Wunused-const-variableNathan Huckleberry
[ Upstream commit a95fb581b144b5e73da382eaedb2e32027610597 ] drivers/clk/clk-qoriq.c:138:38: warning: unused variable 'p5020_cmux_grp1' [-Wunused-const-variable] static const struct clockgen_muxinfo p5020_cmux_grp1 drivers/clk/clk-qoriq.c:146:38: warning: unused variable 'p5020_cmux_grp2' [-Wunused-const-variable] static const struct clockgen_muxinfo p5020_cmux_grp2 In the definition of the p5020 chip, the p2041 chip's info was used instead. The p5020 and p2041 chips have different info. This is most likely a typo. Link: https://github.com/ClangBuiltLinux/linux/issues/525 Cc: clang-built-linux@googlegroups.com Signed-off-by: Nathan Huckleberry <nhuck@google.com> Link: https://lkml.kernel.org/r/20190627220642.78575-1-nhuck@google.com Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-09-19clk: rockchip: Don't yell about bad mmc phases when gettingDouglas Anderson
commit 6943b839721ad4a31ad2bacf6e71b21f2dfe3134 upstream. At boot time, my rk3288-veyron devices yell with 8 lines that look like this: [ 0.000000] rockchip_mmc_get_phase: invalid clk rate This is because the clock framework at clk_register() time tries to get the phase but we don't have a parent yet. While the errors appear to be harmless they are still ugly and, in general, we don't want yells like this in the log unless they are important. There's no real reason to be yelling here. We can still return -EINVAL to indicate that the phase makes no sense without a parent. If someone really tries to do tuning and the clock is reported as 0 then we'll see the yells in rockchip_mmc_set_phase(). Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-16clk: s2mps11: Add used attribute to s2mps11_dt_matchNathan Chancellor
[ Upstream commit 9c940bbe2bb47e03ca5e937d30b6a50bf9c0e671 ] Clang warns after commit 8985167ecf57 ("clk: s2mps11: Fix matching when built as module and DT node contains compatible"): drivers/clk/clk-s2mps11.c:242:34: warning: variable 's2mps11_dt_match' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct of_device_id s2mps11_dt_match[] = { ^ 1 warning generated. This warning happens when a variable is used in some construct that doesn't require a reference to that variable to be emitted in the symbol table; in this case, it's MODULE_DEVICE_TABLE, which only needs to hold the data of the variable, not the variable itself. $ nm -S drivers/clk/clk-s2mps11.o | rg s2mps11_dt_match 00000078 000003d4 R __mod_of__s2mps11_dt_match_device_table Normally, with device ID table variables, it means that the variable just needs to be tied to the device declaration at the bottom of the file, like s2mps11_clk_id: $ nm -S drivers/clk/clk-s2mps11.o | rg s2mps11_clk_id 00000000 00000078 R __mod_platform__s2mps11_clk_id_device_table 00000000 00000078 r s2mps11_clk_id However, because the comment above this deliberately doesn't want this variable added to .of_match_table, we need to mark s2mps11_dt_match as __used to silence this warning. This makes it clear to Clang that the variable is used for something, even if a reference to it isn't being emitted. Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Fixes: 8985167ecf57 ("clk: s2mps11: Fix matching when built as module and DT node contains compatible") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-08-30MLK-22487-2 clk: imx: imx8mm/n: fix pll mux bitPeng Fan
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit ca6495225c6650a45323125f712b50f90f41871e)
2019-08-30MLK-22487-1 clk: imx: clk-pll14xx: unbypass PLL by defaultPeng Fan
When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 47447f63cd800f4c8bfb3f2208ccae014c472a76)
2019-08-30MLK-22489 clk: imx: pll14xx: avoid glitch when set ratePeng Fan
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 2411e1225375920f2f30093f32cac3bbbb7b8dbb)
2019-08-25clk: renesas: cpg-mssr: Fix reset control race conditionGeert Uytterhoeven
[ Upstream commit e1f1ae8002e4b06addc52443fcd975bbf554ae92 ] The module reset code in the Renesas CPG/MSSR driver uses read-modify-write (RMW) operations to write to a Software Reset Register (SRCRn), and simple writes to write to a Software Reset Clearing Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware User's Manuals. However, this may cause a race condition when two devices are reset in parallel: if the reset for device A completes in the middle of the RMW operation for device B, device A may be reset again, causing subtle failures (e.g. i2c timeouts): thread A thread B -------- -------- val = SRCRn val |= bit A SRCRn = val delay val = SRCRn (bit A is set) SRSTCLRn = bit A (bit A in SRCRn is cleared) val |= bit B SRCRn = val (bit A and B are set) This can be reproduced on e.g. Salvator-XS using: $ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done & $ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done & i2c-rcar e6510000.i2c: error -110 : 40000002 i2c-rcar e66d8000.i2c: error -110 : 40000002 According to the R-Car Gen3 Hardware Manual Errata for Rev. 0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware User's Manual, writes to SRCRn do not require read-modify-write cycles. Note that the R-Car Gen2 Hardware User's Manual has not been updated yet, and still says a read-modify-write sequence is required. According to the hardware team, the reset hardware block is the same on both R-Car Gen2 and Gen3, though. Hence fix the issue by replacing the read-modify-write operations on SRCRn by simple writes. Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com> Fixes: 6197aa65c4905532 ("clk: renesas: cpg-mssr: Add support for reset control") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Linh Phung <linh.phung.jy@renesas.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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