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Early versions of this driver used a set of entropy generation parameters
inherited from QorIQ devices. Those parameters were a hardcoded set
based upon internally-suggested values, and worked well on QorIQ. However,
for certain mx6 devices, oscillator values were found to be exceeding
the upper limit, and so RNG instantiation was failing in those cases.
This code improves initialization by (a) making sure the oscillator
divider is set to a known value, and (b) converting the parameter selection
to a symbolic compiler-generated form, instead of using embedded
magic number constants.
The calculation is now based on the definition of RNG4_ENT_CLOCKS_SAMPLE,
which defaults to 1600 unless overridden by something. The lower limit
is then set as /4, and the upper limit set to *8.
Tested-by: Minnick Michael-B21710 <b21710@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch limits AXI pipeline depth to 1 as a workaround for errta
TKT134813, the write
concurrency problem on mx6.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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RNG4 requires a kickstart process to transition into running mode.
In the case that this kickstart process errors, the driver is shut
back down (under the assumption that internal random padding of keys
or data cannot occur).
In an isolated case, the kickstart failed to start the RNG, an error
was returned, and the driver attempted to de-register an RNG function
that never completed, causing a crash. (This is difficult to test for
without manual intervention).
Therefore, amended the driver shutdown process to only de-register
the hardware RNG when an instance kickstarted without error.
This does NOT correct the kickstart problem, only the consequences.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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During a bug search, a review turned up two places where the wrong
direction was used in dma_sync function calls. In practice. these
compiled away to be inconsequential on the platform in question, but
this may not be true on all platforms.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Former versions of this (ARM) branch of this driver reworked the hardware-
readable scatter/gather list to operate as a set of 32-bit integers,
rather than a packed structure of smaller sizes, which cannot burst-read
correctly on a little-endian platform.
Integration of caamhash.c revealed subtle ways in which the ordering of
items written to a hardware s/g list could create bugs, such as the
"final" bit being written to an entry that would later be updated with
a size, inadvertently erasing the bit (e.g. such as sg_to_sec4_sg_last()
before sg_to_sec4_sg()).
Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended descriptor
structs + hardware scatterlists to use kzalloc() instead of kmalloc(), so
as to ensure that residue data would not be ORed in with the correct data.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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This patch will add driver menu support.
And also, for rng don't need to enable clock, we add operation when no
clock is specified for rng.
Signed-off-by: Terry Lv <r65388@freescale.com>
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i.MX6 instantiates a CAAM with a low-power MDHA block, which does not
compute digests larger than 256 bits. Since the driver installs handlers
for hashes longer than 256 bits in several places, added the ability to
read and interpret the CHA version and instantiations registers, and then
only register handlers that it can support.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add SGT error to formerly reserved entry.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Save of DMA size in extended descriptor was missing, thus crashes could
occur during post-request unmapping.
Also, removed lingering DEBUG def that shouldn't have been there.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add API module for asynchronous hashing
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add API module for /dev/hw_random
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add in RNG4 kickstart function
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add cache coherence to externalized key generation
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Last driver revisions began to incorporate optimized mapping functions
for scatter/gather list management, and then centralized them as inlinable
functions usable from multiple modules. Since these became more globally
useful, moved the coupled cache-coherence functions out of the mainline code
and into the inlined ones for simplification.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add in ahash and rng options for build. Note that because of the way
platform devices detect (as opposed to of-based detection), modularization
of API interfaces is suppressed. Once CONFIG_OF is possible, this
can go away.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Descriptor optimizations, misc whitespace fixes.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Inserted explicit initializers for split-out startup and shutdown functions
needed for kernels using platform devices in place of OF-device-tree
initialization and detection.
Also added necessary ahash algorithm list head to driver private storage
block.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add pointer length extensions, non-error-propgation definition.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Split out inline scatter-gather list handlers into an external header,
and moved key generation into standalone source.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Moved scatter-gather list management outside of single API module
in anticipation of multiple API modules which may be switch selectable.
This includes a number of list management optimizations, as well as
some aead descriptor optimizations.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add <md5.h> inclusion for expanded aead processing.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Update scatter/gather definitions to more closely correspond with
those in the QorIQ 1.2 release tree. Note that the definition of
the CAAM-local scatter-gather table for QorIQ/Power-based devices
assumed big-endian, and therefore does not burst-read properly into
an ARM-based little-endian instantiation. Therefore, applied
close-as-practical definitions to at least get close until a merge
can be accomplished.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Added in register changes to enable RNGB initialization when it is present.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Added in era4 additions, and merged in whitespace fixes so as to be
closed to QorIQ 1.2 staged-for-release code base.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Remove unused DECO base pointer to be consistent with staged-for-1.2
QorIQ release.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Fix caam build error when being built as module.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Update internal definition of hardware link table list such that it can
work properly on both big and little endian 32-bit configurations. This
required pointer resizing, reserved-field initialization, and the
combination of both buffer-pool ID and offset fields into a common
32-bit value that can burst-read correctly.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Extend for ARM/iMX6 compatibility, including:
- Cache coherence for all streaming buffer mappings
- Initialization from non-OF-dependent lower-level drivers
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Extend to include support for ARM targets on iMX6 platforms, including:
- platform property detection when OF device properties unavailable
- ring entry direction clarification for DMA API access
- cache coherence for rings
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add non-device-tree platform property detection for driver startup and
initialization for iMX6 family, including clock control, job ring
detection and initialization, and interrupt mapping.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Add register I/O primitives for ARM compatibility.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Include referenced for clock control,
and define "empty" IRQ function that's not provided on ARM platforms.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Differentiate inclusions for OF versus non-OF platforms,
and include clock control subsystems for ARM targets.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Enable MXC devices to select CAAM driver in Kconfig.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
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Backport in current 3.2 code tested on Power for ARM redevelopment.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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upgrade to 2.6.38
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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commit 1ebfefcf37a6e308266a8d786e8cfea0a454058c upstream.
Without CRYPTO_HASH being selected, mv_cesa has a lot of hooks
into undefined exports.
----
MODPOST 81 modules
Kernel: arch/arm/boot/Image is ready
AS arch/arm/boot/compressed/head.o
GZIP arch/arm/boot/compressed/piggy.gzip
CC arch/arm/boot/compressed/misc.o
CC arch/arm/boot/compressed/decompress.o
ERROR: "crypto_ahash_type" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_final" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_register_ahash" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_unregister_ahash" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_update" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_digest" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_setkey" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_alloc_shash" [drivers/crypto/mv_cesa.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
make: *** Waiting for unfinished jobs....
----
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit f8f54e190ddb4ed697036b60f5e2ae6dd45b801c upstream.
Broken by commit 6ef84509f3d439ed2d43ea40080643efec37f54f for users
passing a request with non-zero 'nbytes' field, like e.g. testmgr.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit 274252862f386b7868f35bf5ceaa5391a8ccfdf3 upstream.
This was broken by commit 7759995c75ae0cbd4c861582908449f6b6208e7a (yes,
myself). The basic problem here is since the digest state is only saved
after the last chunk, the state array is only valid when handling the
first chunk of the next buffer. Broken since linux-3.0.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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setkey allocates 16 bytes (CAAM_CMD_SZ *
DESC_AEAD_SHARED_TEXT_LEN) shy of what is needed to
store the shared descriptor, resulting in memory
corruption. Fix this.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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The registration of an ap device will be skipped, if the device type
probing fails.
Add names of current crypto adapters to the Kconfig help.
Signed-off-by: Holger Dengler <hd@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (45 commits)
crypto: caam - add support for sha512 variants of existing AEAD algorithms
crypto: caam - remove unused authkeylen from caam_ctx
crypto: caam - fix decryption shared vs. non-shared key setting
crypto: caam - platform_bus_type migration
crypto: aesni-intel - fix aesni build on i386
crypto: aesni-intel - Merge with fpu.ko
crypto: mv_cesa - make count_sgs() null-pointer proof
crypto: mv_cesa - copy remaining bytes to SRAM only when needed
crypto: mv_cesa - move digest state initialisation to a better place
crypto: mv_cesa - fill inner/outer IV fields only in HMAC case
crypto: mv_cesa - refactor copy_src_to_buf()
crypto: mv_cesa - no need to save digest state after the last chunk
crypto: mv_cesa - print a warning when registration of AES algos fail
crypto: mv_cesa - drop this call to mv_hash_final from mv_hash_finup
crypto: mv_cesa - the descriptor pointer register needs to be set just once
crypto: mv_cesa - use ablkcipher_request_cast instead of the manual container_of
crypto: caam - fix printk recursion for long error texts
crypto: caam - remove unused keylen from session context
hwrng: amd - enable AMD hw rnd driver for Maple PPC boards
hwrng: amd - manage resource allocation
...
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In doing so, sha512 sized keys would not fit with the current
descriptor inlining mechanism, so we now calculate whether keys
should be referenced instead by pointers in the shared descriptor.
also, use symbols for descriptor text lengths, and, ahem, unmap and
free key i/o memory in cra_exit.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Key sharing is enabled by default in the shared descriptor.
Using CBC decrypt, AES has to alter the key in order to decrypt.
During high traffic decryption rates, i.e, when sharing starts to
take place, we need to use a different OPERATION option to tell AES
that the key was already altered by the PRIOR descriptor - we need
the following kind of logic:
if ( shared )
operation where AES uses decryption key (DK=1)
else
operation where AES uses encryption key (DK=0)
this patch implements this logic using a conditional and
a non-conditional local jump within the decryption job
descriptor.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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this fixes a build error since cryptodev-2.6 got rebased
to include commit d714d1979d7b4df7e2c127407f4014ce71f73cd0
"dt: eliminate of_platform_driver shim code".
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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This also makes the dummy scatterlist in mv_hash_final() needless, so
drop it.
XXX: should this routine be made pulicly available? There are probably
other users with their own implementations.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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On one hand, the digest state registers need to be set only when
actually using the crypto engine. On the other hand, there is a check
for ctx->first_hash in mv_process_hash_current() already, so use that.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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