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path: root/drivers/crypto
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2017-12-21Merge tag 'v4.9.67' into 4.9-1.0.x-imx-fixes-stable-mergeMarcel Ziswiler
This is the 4.9.67 stable release Resolved conflicts: arch/arm/boot/dts/imx6sx-sdb.dts drivers/dma/imx-sdma.c drivers/mmc/core/host.c drivers/usb/chipidea/otg.c sound/soc/fsl/fsl_ssi.c This merge also reverts commit 3a654a85932f ("dmaengine: imx-sdma - correct the dma transfer residue calculation"). The downstream kernel seems to use different structures and already use buf_ptail in its calculation.
2017-11-30crypto: marvell - Copy IVDIG before launching partial DMA ahash requestsRomain Perier
[ Upstream commit 8759fec4af222f338d08f8f1a7ad6a77ca6cb301 ] Currently, inner IV/DIGEST data are only copied once into the hash engines and not set explicitly before launching a request that is not a first frag. This is an issue especially when multiple ahash reqs are computed in parallel or chained with cipher request, as the state of the request being computed is not updated into the hash engine. It leads to non-deterministic corrupted digest results. Fixes: commit 2786cee8e50b ("crypto: marvell - Move SRAM I/O operations to step functions") Signed-off-by: Romain Perier <romain.perier@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: <stable@vger.kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-15crypto: vmx - disable preemption to enable vsx in aes_ctr.cLi Zhong
[ Upstream commit 7dede913fc2ab9c0d3bff3a49e26fa9e858b0c13 ] Some preemptible check warnings were reported from enable_kernel_vsx(). This patch disables preemption in aes_ctr.c before enabling vsx, and they are now consistent with other files in the same directory. Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08crypto: ccp - Set the AES size field for all modesGary R Hook
[ Upstream commit f7cc02b3c3a33a10dd5bb9e5dfd22e47e09503a2 ] Ensure that the size field is correctly populated for all AES modes. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-05crypto: talitos - fix hashingLEROY Christophe
commit 886a27c0fc8a34633aadb0986dba11d8c150ae2e upstream. md5sum on some files gives wrong result Exemple: With the md5sum from libkcapi: c15115c05bad51113f81bdaee735dd09 test With the original md5sum: bbdf41d80ba7e8b2b7be3a0772be76cb test This patch fixes this issue Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-05crypto: talitos - fix sha224LEROY Christophe
commit afd62fa26343be6445479e75de9f07092a061459 upstream. Kernel crypto tests report the following error at startup [ 2.752626] alg: hash: Test 4 failed for sha224-talitos [ 2.757907] 00000000: 30 e2 86 e2 e7 8a dd 0d d7 eb 9f d5 83 fe f1 b0 00000010: 2d 5a 6c a5 f9 55 ea fd 0e 72 05 22 This patch fixes it Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-05crypto: talitos - Don't provide setkey for non hmac hashing algs.LEROY Christophe
commit 56136631573baa537a15e0012055ffe8cfec1a33 upstream. Today, md5sum fails with error -ENOKEY because a setkey function is set for non hmac hashing algs, see strace output below: mmap(NULL, 378880, PROT_READ, MAP_SHARED, 6, 0) = 0x77f50000 accept(3, 0, NULL) = 7 vmsplice(5, [{"bin/\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"..., 378880}], 1, SPLICE_F_MORE|SPLICE_F_GIFT) = 262144 splice(4, NULL, 7, NULL, 262144, SPLICE_F_MORE) = -1 ENOKEY (Required key not available) write(2, "Generation of hash for file kcap"..., 50) = 50 munmap(0x77f50000, 378880) = 0 This patch ensures that setkey() function is set only for hmac hashing. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-27crypto: ccp - Fix XTS-AES-128 support on v5 CCPsGary R Hook
commit e652399edba99a5497f0d80f240c9075d3b43493 upstream. Version 5 CCPs have some new requirements for XTS-AES: the type field must be specified, and the key requires 512 bits, with each part occupying 256 bits and padded with zeroes. Signed-off-by: Gary R Hook <ghook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-08-24crypto: ixp4xx - Fix error handling path in 'aead_perform()'Herbert Xu
commit 28389575a8cf933a5f3c378556b9f4d3cce0efd2 upstream. In commit 0f987e25cb8a, the source processing has been moved in front of the destination processing, but the error handling path has not been modified accordingly. Free resources in the correct order to avoid some leaks. Fixes: 0f987e25cb8a ("crypto: ixp4xx - Fix false lastlen uninitialised warning") Reported-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-21crypto: caam - fix signals handlingHoria Geantă
commit 7459e1d25ffefa2b1be799477fcc1f6c62f6cec7 upstream. Driver does not properly handle the case when signals interrupt wait_for_completion_interruptible(): -it does not check for return value -completion structure is allocated on stack; in case a signal interrupts the sleep, it will go out of scope, causing the worker thread (caam_jr_dequeue) to fail when it accesses it wait_for_completion_interruptible() is replaced with uninterruptable wait_for_completion(). We choose to block all signals while waiting for I/O (device executing the split key generation job descriptor) since the alternative - in order to have a deterministic device state - would be to flush the job ring (aborting *all* in-progress jobs). Fixes: 045e36780f115 ("crypto: caam - ahash hmac support") Fixes: 4c1ec1f930154 ("crypto: caam - refactor key_gen, sg") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-21crypto: caam - properly set IV after {en,de}cryptDavid Gstir
commit 854b06f768794cd664886ec3ba3a5b1c58d42167 upstream. Certain cipher modes like CTS expect the IV (req->info) of ablkcipher_request (or equivalently req->iv of skcipher_request) to contain the last ciphertext block when the {en,de}crypt operation is done. This is currently not the case for the CAAM driver which in turn breaks e.g. cts(cbc(aes)) when the CAAM driver is enabled. This patch fixes the CAAM driver to properly set the IV after the {en,de}crypt operation of ablkcipher finishes. This issue was revealed by the changes in the SW CTS mode in commit 0605c41cc53ca ("crypto: cts - Convert to skcipher") Signed-off-by: David Gstir <david@sigma-star.at> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-21crypto: atmel - only treat EBUSY as transient if backlogGilad Ben-Yossef
commit 1606043f214f912a52195293614935811a6e3e53 upstream. The Atmel SHA driver was treating -EBUSY as indication of queueing to backlog without checking that backlog is enabled for the request. Fix it by checking request flags. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-21crypto: talitos - Extend max key length for SHA384/512-HMAC and AEADMartin Hicks
commit 03d2c5114c95797c0aa7d9f463348b171a274fd4 upstream. An updated patch that also handles the additional key length requirements for the AEAD algorithms. The max keysize is not 96. For SHA384/512 it's 128, and for the AEAD algorithms it's longer still. Extend the max keysize for the AEAD size for AES256 + HMAC(SHA512). Fixes: 357fb60502ede ("crypto: talitos - add sha224, sha384 and sha512 to existing AEAD algorithms") Signed-off-by: Martin Hicks <mort@bork.org> Acked-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-15crypto: caam - fix gfp allocation flags (part I)Horia Geantă
commit 42cfcafb91dabb0f9d9e08396c39824535948c67 upstream. Changes in the SW cts (ciphertext stealing) code in commit 0605c41cc53ca ("crypto: cts - Convert to skcipher") revealed a problem in the CAAM driver: when cts(cbc(aes)) is executed and cts runs in SW, cbc(aes) is offloaded in CAAM; cts encrypts the last block in atomic context and CAAM incorrectly decides to use GFP_KERNEL for memory allocation. Fix this by allowing GFP_KERNEL (sleeping) only when MAY_SLEEP flag is set, i.e. remove MAY_BACKLOG flag. We split the fix in two parts - first is sent to -stable, while the second is not (since there is no known failure case). Link: http://lkml.kernel.org/g/20170602122446.2427-1-david@sigma-star.at Reported-by: David Gstir <david@sigma-star.at> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-13MLK-14765: Enable DCP SHA workaround on all platformsRadu Solea
Remove variant restriction for DCP SHA workaround. All integrations of DCP seem affected. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-07-05MA-9807: Fix ecb(aes) use without an IVRadu Solea
CAAM aes modes share descriptors, because of this CAAM requires an IV for ECB. ECB does not need an IV and users do not have to pass valid IV vectors. To allow correct usage with minimum impact to the driver a zero IV is provided by the driver for ECB operations that need it. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-20MLK-14765: Fix DCP Aes timeout issues when used with CTSRadu Solea
The DCP driver does not obey cryptlen, when doing CTS this results in passing to hardware input stream lengths which are not multiple of block size. This causes the hw to misbehave. Also not honoring cryptlen makes CTS fail. A check was introduced to prevent future erroneous stream lengths from reaching the hardware. Code which is splitting the input stream in internal DCP pages was changed to obey cryptlen. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-20MLK-14765: Fix DCP SHA null hashes and output lengthRadu Solea
On imx6sl and imx6ull DCP writes at least 32 bytes in the output buffer instead of hash length as documented. Add intermediate buffer to prevent write out of bounds. When requested to produce null hashes DCP fails to produce valid output. Add software workaround to bypass hardware and return valid output. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-09MLK-14611 Fix xcbc unkeyed registrationRadu Solea
AES is a keyed algorithm, XCBC-AES needs a key for operation, this patch prevents the registration of AES-based transforms as unkeyed operations. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-09MLK-14284 Fix CAAM Errata err005766 handlingRadu Solea
Update ERA detection code to check 3 sources CCBVID, CAAMVID and the device tree. Fix bit handling of CAAMVID data to obtain correct results. Remove default device tree values. Update errata handling to target known affected platforms. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-09MLK-14611 Fix CBC mode support by returning a correct IVRadu Solea
Current CBC mode does not return the last cyphertext block as IV for operation chaining. CTS fails because of incorrect IV. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-09MLK-14611 Add DES key complexity validationRadu Solea
Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-08Add missing NULL checks in CAAM smRadu Solea
Missing NULL checks in CAAM sm_store and sm_test cause kernel crashes if caam init fails. Signed-off-by: Radu Solea <radu.solea@nxp.com>
2017-06-08MLK-13779 crypto: caam - initialize kslock spinlockOctavian Purdila
Fixes the following lockdep message: INFO: trying to register non-static key. the code is fine but needs lockdep annotation. turning off the locking correctness validator. CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.30-02225-g55e4b9e #8 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [<800162b0>] (unwind_backtrace) from [<80012ba0>] (show_stack+0x10/0x14) [<80012ba0>] (show_stack) from [<808d09d0>] (dump_stack+0xa8/0xd4) [<808d09d0>] (dump_stack) from [<8007aed0>] (__lock_acquire+0x1eb0/0x2224) [<8007aed0>] (__lock_acquire) from [<8007b840>] (lock_acquire+0xa4/0xd0) [<8007b840>] (lock_acquire) from [<808dc28c>] (_raw_spin_lock+0x3c/0x4c) [<808dc28c>] (_raw_spin_lock) from [<80666724>] (sm_keystore_slot_alloc+0x24/0x74) [<80666724>] (sm_keystore_slot_alloc) from [<806677c8>] (caam_sm_example_init+0x1ec/0xb68) [<806677c8>] (caam_sm_example_init) from [<80c6ff48>] (caam_sm_test_init+0x50/0x58) [<80c6ff48>] (caam_sm_test_init) from [<80009770>] (do_one_initcall+0x8c/0x1d8) [<80009770>] (do_one_initcall) from [<80c26dc8>] (kernel_init_freeable+0x144/0x1e4) [<80c26dc8>] (kernel_init_freeable) from [<808cbff0>] (kernel_init+0x8/0xe8) [<808cbff0>] (kernel_init) from [<8000f618>] (ret_from_fork+0x14/0x3c) Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com> Reviewed-by: Dan Douglass <dan.douglass@nxp.com>
2017-06-08MLK-13095 DCP driver doesn't initialize the DCP clockDan Douglass
Added clock enable and disable to the probe and remove functions where appropriate. Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
2017-06-08MLK-13073 crypto: dcp: Add DCP support for i.mx6Dan Douglass
Enable DCP support for imx6 series. Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
2017-05-20crypto: ccp - Change ISR handler method for a v5 CCPGary R Hook
commit 6263b51eb3190d30351360fd168959af7e3a49a9 upstream. The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-20crypto: ccp - Change ISR handler method for a v3 CCPGary R Hook
commit 7b537b24e76a1e8e6d7ea91483a45d5b1426809b upstream. The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-20crypto: ccp - Disable interrupts early on unloadGary R Hook
commit 116591fe3eef11c6f06b662c9176385f13891183 upstream. Ensure that we disable interrupts first when shutting down the driver. Signed-off-by: Gary R Hook <ghook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-20crypto: ccp - Use only the relevant interrupt bitsGary R Hook
commit 56467cb11cf8ae4db9003f54b3d3425b5f07a10a upstream. Each CCP queue can product interrupts for 4 conditions: operation complete, queue empty, error, and queue stopped. This driver only works with completion and error events. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-14crypto: caam - fix error path for ctx_dma mapping failureHoria Geantă
commit 87ec02e7409d787348c244039aa3536a812dfa8b upstream. In case ctx_dma dma mapping fails, ahash_unmap_ctx() tries to dma unmap an invalid address: map_seq_out_ptr_ctx() / ctx_map_to_sec4_sg() -> goto unmap_ctx -> -> ahash_unmap_ctx() -> dma unmap ctx_dma There is also possible to reach ahash_unmap_ctx() with ctx_dma uninitialzed or to try to unmap the same address twice. Fix these by setting ctx_dma = 0 where needed: -initialize ctx_dma in ahash_init() -clear ctx_dma in case of mapping error (instead of holding the error code returned by the dma map function) -clear ctx_dma after each unmapping Fixes: 32686d34f8fb6 ("crypto: caam - ensure that we clean up after an error") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-18crypto: caam - fix invalid dereference in caam_rsa_init_tfm()Horia Geantă
commit 33fa46d7b310e06d2cb2ab5417c100af120bfb65 upstream. In case caam_jr_alloc() fails, ctx->dev carries the error code, thus accessing it with dev_err() is incorrect. Fixes: 8c419778ab57e ("crypto: caam - add support for RSA algorithm") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-18crypto: caam - fix RNG deinstantiation error checkingHoria Geantă
commit 40c98cb57cdbc377456116ad4582c89e329721b0 upstream. RNG instantiation was previously fixed by commit 62743a4145bb9 ("crypto: caam - fix RNG init descriptor ret. code checking") while deinstantiation was not addressed. Since the descriptors used are similar, in the sense that they both end with a JUMP HALT command, checking for errors should be similar too, i.e. status code 7000_0000h should be considered successful. Fixes: 1005bccd7a4a6 ("crypto: caam - enable instantiation of all RNG4 state handles") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-30crypto: ccp - Assign DMA commands to the channel's CCPGary R Hook
commit 7c468447f40645fbf2a033dfdaa92b1957130d50 upstream. The CCP driver generally uses a round-robin approach when assigning operations to available CCPs. For the DMA engine, however, the DMA mappings of the SGs are associated with a specific CCP. When an IOMMU is enabled, the IOMMU is programmed based on this specific device. If the DMA operations are not performed by that specific CCP then addressing errors and I/O page faults will occur. Update the CCP driver to allow a specific CCP device to be requested for an operation and use this in the DMA engine support. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-02-23MLK-11922 i.mx6: Linux 3.14.28 CAAM & SNVS enabled by default.ulises
JTAG, DS-5 attachment causes exceptions Added properties to device tree, in order to enable and disable alarms. The following are the available alarms: -JTAG active -WatchDOG 2 reset -Internal Boot -External Tamper Detection pad
2017-02-23MLK-12312: CAAM hash algorithms fail registration during initializationRussell King
Fix cherry-picked from 5ec908319ab53072d3a2188e62ed2e5d7b846951 crypto: caam - only export the state we really need to export Avoid exporting lots of state by only exporting what we really require, which is the buffer containing the set of pending bytes to be hashed, number of pending bytes, the context buffer, and the function pointer state. This reduces down the exported state size to 216 bytes from 576 bytes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-02-23MLK-12302 caam: Secure Memory platform device creation crashesDan Douglass
There is new flag that is checked in of_platform_device_create(). The flag is cleared prior to the call now so the device creates successfully. Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
2017-02-23MLK-11360-01 crypto: caam_snvs: add snvs clock managementFugang Duan
caam_snvs driver involves snvs HP registers access that needs to enable snvs clock source. The patch add the clock management. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-11103 Missing register in Secure memory configuration v1Ulises Cardenas
Added missing reserved register for caam_secure_mem_v1 struct Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-11020: arm: imx: caam: imx7d caam_aclk clock dependencyAdrian Alonso
* Add caam_aclk clock root dependency, imx7d caam ip module needs caam_aclk and caam_ipg clock signals to operate add additional clock signal. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com> [Octavian: since the clk API skips NULL args use a single disable label] Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
2017-02-23MLK-10978-1 ARM: imx6ul: Add CAAM support for i.mx6ulDan Douglass
There are only 3 CAAM clocks that are required for i.mx6ul. Adding logic to enable only the required clocks based on the device tree compatibility node. Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-10897-1 ARM: imx7d: Add CAAM support for i.mx7dDan Douglass
CAAM only has a single clock in i.mx7d. Logic was added to initialize only the single clock. The Secure Memory registers moved in CAAM era included in i.mx7d. This required changes to support access to two different versions of the register map. The registers are access through a data structure that overlay the register region. Two new Secure Memory register structures were created to support the different versions. Logic was also added to determine which version is implemented based on the CAAM era, and access functions were added to support register access to the Secure Memory Command and Status registers. Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9769-23 Replace SECVIO of_irq_to_resource() with irq_of_parse_and_map()Victoria Milhoan
Replace of_irq_to_resource() in the SECVIO module with the simpler equivalent irq_of_parse_and_map(). Also, add error checking to to the SECVIO and Job Ring modules. Based on upstream commit f7578496a671a96e501f16a5104893275e32c33a. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-10036 Freescale CAAM: Add support for DSM with Mega/Fast mix onVictoria Milhoan
This patch allows CAAM to be enabled as a wakeup source for the Mega/Fast mix domain. If CAAM is enabled as a wakeup source, it will continue to be powered on across Deep Sleep Mode (DSM). This allows CAAM to be functional after the system resumes from DSM. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> (cherry picked from commit 290744e3b40a563319324e234fa5a65b49fd4d82) Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9971 Add XCBC-AES support for CAAM in i.MX6 familyWinston Hudson (b45308)
Add XCBC-AES support to the CAAM crypto accelerator core in the i.MX6 family of SoC devices. Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ). Thus the property names are often tied to the sec-4.0+ nomenclature. Signed-off-by: Winston Hudson (b45308) <winston.h.hudson@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9951 Update CAAM driver era interfaceVictoria Milhoan
Add more CAAM era values to the CAAM driver's caam_get_era() function. Read only 32 bits of data since the data required to identify the IP_ID and MAJ_REV is located in the first 32 bits of the register. And, update the function for use with ARM/Little Endian devices. [<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> (cherry picked from commit 6050d7faf2d0c063195aa9454c130548a9f8058f) Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9710-5 Unregister Secure Memory platform device upon shutdownVictoria Milhoan
Unregister Secure Memory platform device when the Secure Memory module is shut down. This allows the Secure Memory module to be inserted again successfully. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> (cherry picked from commit 785456f38234e64618ee9c74ab4258f39f00e73c) Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9769-20 Limit AXI pipeline to a depth of one in CAAM for i.MX6 devicesVictoria Milhoan (b42089)
i.MX6 devices have an issue wherein AXI bus transactions may not occur in the correct order. This isn't a problem running single descriptors, but can be if running multiple concurrent descriptors. Reworking the CAAM driver to throttle to single requests is impractical, so this patch limits the AXI pipeline to a depth of one (from a default of four) to preclude this situation from occurring. Signed-off-by: Victoria Milhoan (b42089) <vicki.milhoan@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9769-19 Add ARC4-ECB support for CAAM in i.MX6 familyWinston Hudson
Adds ARC4-ECB Mode support to the CAAM crypto accelerator core in the i.MX6 family of SoC devices. Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ). Thus the property names are often tied to the sec-4.0+ nomenclature. Signed-off-by: Winston Hudson (b45308) <winston.h.hudson@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
2017-02-23MLK-9769-18 Add 3DES-ECB-EDE support for CAAM in i.MX6 familyWinston Hudson (b45308)
Adds 3DES-ECB-EDE Mode support to the CAAM crypto accelerator core in the i.MX6 family of SoC devices. Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ). Thus the property names are often tied to the sec-4.0+ nomenclature. Signed-off-by: Winston Hudson (b45308) <winston.h.hudson@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-24 21:06:25 +0000