Age | Commit message (Collapse) | Author |
|
The 1.8V quirk also affected the internal eMMC which disabled newer
modes such as SDR50, SDR104 and DDR50. This in turn lead to an
out of spec usage since the clock was still 50MHz.
By creating a no_1v8 field in the platform data we can now enable
this work around on a per-instance basis. Hence we enable the
quirk only on the controllers which are connected to the external
SD-slots.
|
|
Fix the following build issue introduced by commit
5cfcbc23d116927a7ae8d5b67baeacf2905b21f9 if neither
CONFIG_MACH_APALIS_T30 nor CONFIG_MACH_COLIBRI_T30 is defined as in
case of e.g. the Colibri T20:
drivers/mmc/host/sdhci-tegra.c:951:2:
error: expected expression before '.' token
|
|
SDR12, SDR25, SDR50, SDR104 and DDR50 all require 1.8V signalling which
our current T30 designs can't do. Newer cards will fail as follows:
Kingston 32GB microSDHC class 10
[ 69.000280] mmc1: error -84 whilst initialising SD card
SanDisk Mobile Ultra 8GB microSDHC I
[ 28.289174] mmc1: error -110 whilst initialising SD card
This patch activates a quirk which signals our lack of 1.8V support.
|
|
The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v
capable, and it truthfully reports so in its capabilities. This
alternate voltage is used for driving new "UHS-I" SD cards at their
full speed.
However, what the controller doesn't know is that the motherboard
physically doesn't have a 1.8v supply available.
Add a quirk so that systems such as this one can override disable
1.8v support, adding support for UHS-I cards (by running them at
3.3v).
This avoids a problem where the system would first try to run the
card at 1.8v, fail, and then not be able to fully reset the card
to retry at the normal 3.3v voltage.
This is more appropriate than using the MISSING_CAPS quirk, which
is intended for cases where the SDHCI controller is actually lying
about its capabilities, and would force us to somehow override both
caps words from another source.
Signed-off-by: Daniel Drake <dsd@laptop.org>
Reviewed-by: Philip Rakity <prakity@nvidia.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
|
|
Conflicts:
arch/arm/mach-tegra/tegra3_usb_phy.c
arch/arm/mach-tegra/usb_phy.c
drivers/usb/gadget/tegra_udc.c
drivers/usb/otg/Makefile
drivers/video/tegra/fb.c
sound/soc/tegra/tegra_pcm.c
|
|
Hack to avoid extensive warning messages from Redpine Signals LiteFi
driver due to unaligned DMA accesses.
|
|
The gpio mode of pin is configured when setting
direction and hence this call is no more required.
Change-Id: I2c9bce83a283f6ef45754075cf3b7b1bc5c1d9ac
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/119612
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
- Add compilation flag to treat warning as error
- Modified sdhci-tegra.c to remove compile warning
bug 949219
Change-Id: I704ea95e3b8ca8862482b6793b71ca4e5114f832
Signed-off-by: schowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/118036
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Without card clock, inband interrupt is not working on
some wifi chips.
Bug 981683
This reverts commit b31946b34507209f26c6d709e23fd1c0cedd25f8.
Change-Id: I2dd86edb2445bd6db7917adf509b7a018d31aaed
Reviewed-on: http://git-master/r/110839
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: I6f2266ac5b6bd9585272958b4b8a89af1b3cdffb
Reviewed-on: http://git-master/r/119009
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
|
|
If eMMC sleep support is enabled, set MMC_PM_KEEP_POWER
to avoid host power off and power on. Instead, restore
the host context in resume.
Bug 1007644
Bug 936069
Change-Id: I74578bb1f9e297b3af6bd79b9215364334984836
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/118913
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
For SDIO devices, MMC_PM_KEEP_POWER would be set
by wifi driver during suspend. It need not be set
by default.
Bug 1011349
Change-Id: I779a438b45afed2cc0fd7283d89c24e9049cfe39
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/118954
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
|
|
Without the card clock, inband interrupt is not working on
some wifi chips.
Bug 981683
This reverts commit 0467657691ba046b492504272baf7c626d9a3713.
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/110826
(cherry picked from commit 33c8e504328387097ed0160082cce6b36b994bd8)
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: I6683720a9bda1f779a63133d8ca64a024c5d8a08
Reviewed-on: http://git-master/r/116707
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Disable the normal interrupts signalling before
tuning and enable it only after the entire tuning
process is done.
Bug 860102
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/111589
(cherry picked from commit 15a97f33f6cf1fc1c25441142f69f62ce5f7029b)
Change-Id: I9eba9af65a50928dc4bb475e06cbf401963751bc
Reviewed-on: http://git-master/r/116433
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
The host clock configuration in SDR50 mode is
incorrectly grouped with DDR50 mode due to which
DDR50 mode clock limits are wrongly applied even
in SDR50 mode.
Bug 965298
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/111566
(cherry picked from commit 2ad290d477e8198bace22d2623856555f07b9bf9)
Change-Id: I5d3a446e39a349209e5842d385c1b728bfb7012e
Reviewed-on: http://git-master/r/116428
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
This is a WAR solution that allows for the turning on
SD DPD feature.
The original issue is that enabling SD DPD immediately after device comes
out of LP0 causes ULPI disconnect. The root cause of that is
not known.
The WAR is to delay the enabling of SD DPD for 100ms after
device comes out of LP0.
Bug 929628
Change-Id: I946771a8e92459464ce571295f96f197db25c061
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
(cherry picked from commit beba2b34af7ff9313aed074342b9bb86b12620a8)
Reviewed-on: http://git-master/r/113391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
If there are errors happened in sdhci_suspend_host, handle it so that
when the function returns with an error, the host's behaviour is the
same before this function call, e.g. card detection is enabled and
tuning timer is active, etc.
Signed-off-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Aaron Lu <aaron.lu@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit 38a60ea2e7b33ab33ee11d6ef527f259edb102cf)
Bug 984811
Change-Id: I532c3914cecf63291a23baa669c650b4ac5448e4
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/106351
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
check for platform limits before setting the voltage
Bug 979504
Change-Id: Iea78be15d6a0eea0f4344c9b78ff9366f4759af8
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/104711
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Merges of dma changes from mainline reported conflict and
it was not got resolved properly.
Fix the resolution issue.
Change-Id: I7edc5effc0b9a61363e77e6cc39eb62e315396d0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102590
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
|
|
Adding a new config option and enabling background ops in driver.
Correcting the EXT_CSD byte that needs to be written in order to
trigger background ops in the MMC firmware.
Bug 847037.
Change-Id: Ibc517540cab43fa5070b142a416f6b67f2f7e7be
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/99117
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Set the eMMC ddr mode clock dynamically based on emc
clock rate. If ddr clock limit is specified and the emc
clock is less than max emc freq, then limit emmc ddr
clk. If not, set the max eMMC ddr clock.
Bug 967719
Change-Id: I9f70077c4ac4bb1f3e6d894fcb8420b1aba284dd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/100579
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
In SDR50 mode, set the controller clock to double
the requested clock to ensure that the core voltage
is maintained at a min of 1.2V.
Bug 965298
Change-Id: I557a07de97efd6b44f812a11da657e03d3ddefd0
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/101522
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Some boards don't have a vddio regulator for few rails hence not getting
the regulator handle. And we assume that those rails are always powered.
Hence rephrased the error message and lowered the loglevel to KERN_INFO.
Bug 976177
Change-Id: I92b82f75934eaf7137584a625065e3389b6ae1b7
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/100490
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
The CL disables SDIO card clock when idle for Tegra 3 only.
Bonus: conditional build for some tegra 3 functionalities.
Bug 975541
Change-Id: I097c4771f3565bf9137d7854ada10c1fe8535056
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/99707
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Peer Chen <pchen@nvidia.com>
|
|
enable MMC_PM_IGNORE_PM_NOTIFY for all sd instances
Bug 956238
Bug 932086
Change-Id: I4d455e480eabace403719f1813d97abfa4d01924
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/96071
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
Disable card clock before disabling internal clock to
ensure that there are no abnormal clock waveforms.
Bug 947058
Change-Id: I98a3f7f63b4380b62bead05f1018d3cddc0ac217
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/95396
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Disable SDIO card clock when there are no commands/
data transfers on the SD bus.
Bug 958954
Bug 955742
Bug 952344
Change-Id: I7390be0406f7e46c0eb88ede2ae6f904b2181306
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/95390
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
bug 949219
Change-Id: I5942ba86bd1cbe1f1bd06a7c9f51a10d83e6cabb
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/92819
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Enable embedded sdio code, iff MMC_EMBEDDED_SDIO
Kconfig is on.
Bug 956238
Change-Id: I16539f5cad5fc66082af2f569ea36a54c12457e3
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/90655
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Add inline wrappers for device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to hide new parameter from current users of affected interfaces.
Convert current users to use new wrappers instead of direct calls.
Suggested by Russell King [https://lkml.org/lkml/2012/2/3/269].
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline commit
16052827d98fbc13c31ebad560af4bd53e2b4dd5
Change-Id: I929a49556539621a0546829e88b3caa498c94be2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/94463
|
|
Initialize pm_caps and pm_flags through platform
data.
Bug 956238
Change-Id: I400f6e92541fa2e63ccc7f829e204d5eef4697fc
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/90790
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>
|
|
Enable quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION.
Also, implemented tegra_sdhci_get_cd() to return
the card presence status.
Bug 948943
Change-Id: I42eed23f951304e331a235f5a9199b70ba5e96b5
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/87766
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Add get_cd callback in the host ops to get the
card presence status incase SDHCI_QUIRK_BROKEN_
CARD_DETECTION is enabled.
Bug 948943
Change-Id: I788d9e907920a0aeb79784751ec0df25bc2a72d6
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/87765
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
if SDHCI_QUIRK_NO_HISPD_BIT is set in host->quirks,
don't set SDHCI_CTRL_HISPD in sdhci_host_control register.
bug 929985
Signed-off-by: Harry Hong <hhong@nvidia.com>
Reviewed-on: http://git-master/r/79933
(cherry picked from commit 194670660af90b2bb7bc0efea920332459296141)
Change-Id: I7b5f58f5078886309610e9e4cc2bad83f0788168
Reviewed-on: http://git-master/r/87704
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Bug 942826
Change-Id: Ie782f17c51e78994e0fc96da3fbbe2e6592f58dc
Signed-off-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-on: http://git-master/r/84697
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
This bit should always be 0 according to TRM.
Bug 929985
Signed-off-by: Harry Hong <hhong@nvidia.com>
Reviewed-on: http://git-master/r/79975
(cherry picked from commit 9371d04b4f9d79f1e03e60120bf1bba28af77d4b)
Change-Id: I225d6b5442f63809a77ce92d9cbd152dc4112ac4
Reviewed-on: http://git-master/r/87640
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
MMC_PM_KEEP_POWER was used on the wrong structure member, which might
cause card interrupt lost during suspend/resume
Bug 936503
Change-Id: Ib42d7a5ba27c0175e944223967c416a3c80802dd
Signed-off-by: David Schalig <dschalig@nvidia.com>
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/83011
Reviewed-on: http://git-master/r/86020
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This reverts commit caa6566d4fb8539d09276c1bcb818444af675624.
MMC_PM_KEEP_POWER should be used only for sdio as power-on/off code is
implemented only for sdio.
This may also create regression in power.
Bug 938011
Bug 943131
Change-Id: I41a29acb3dd6f3396c97ab78f9704f9b39359675
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/85213
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
|
|
In case of non standard clock, preset value
should not be enabled from sdhci driver as
it would make clock divider programming in-
effective.
Bug 937318
Change-Id: I5eaeab538a4978dd8c03501c3dcba2e8a92eea59
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/84807
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
Tegra sdmmc controllers support fixed sampling
frequency tuning. Also, frequency tuning is used
to find the ideal tap delay value which ensures
reliable high speed data transfers. Added support
for the same. In SDR50 mode, setting controller clk
rate to 208MHz as lower clk rates result in CRC
errors.
Bug 919232
Originally reviewed on: http://git-master/r/72596
Change-Id: I8825b4bdbc8533005bc76c54f5d1660f18304e4d
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/77798
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
During resume mmc_power_up is not necessary for eMMC
Bug 932606
Change-Id: I6dd6e7c4f5582ecca8b9c459e3537b05cce69e69
Signed-off-by: naveen kumar arepalli<naveenk@nvidia.com>
Reviewed-on: http://git-master/r/83709
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
Enable the regulator with out any dependency on slot
regulator
Bug 932739
Signed-off-by: vjagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/78745
(cherry picked from commit 83d256fe3c269f59436a7cc08e46235ab5c067c8)
Change-Id: I80fbaef6b76fd4bb7990c29499a62abfe46e5150
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/82711
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
enabling quirk *SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO* for not to
calculate max discard timeout.
bug 930767
Change-Id: Id2ca4fd202961d1997c9269eb0d437a6fca241cf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/79840
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
Adding SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO for not to calculate
max_discard_to which is deviation in setting max_discard.
For some host controllers, combination of
1) calculated non-zero value of max_discard_to and
2) erase_group_def not set
can result into setting max_discard value to pref_erase in
sectors which is very less, so it takes long time for erase.
With this change host controller can specify to calculate
max_discard_to and based on that max_discard value will be set.
bug 930767
Change-Id: I2c64ef8a6821620f2a65c06e25d2af68e3554a75
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/79839
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
|
|
tegra_sdhci_suspend() had code to disable the same regulators
twice. Remove one instance of the code to avoid warnings
during system suspend.
Change-Id: I71789b40a6d5e5c500c57b8323b9f4bc79634886
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78682
Reviewed-by: Automatic_Commit_Validation_User
|
|
Enabling power rails when the card is present
which reduces power consumption
Bug 924888
Reviewed-on: http://git-master/r/75653
Change-Id: If9cbd02b49821954646845bd889501e9159c7b8c
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78023
Reviewed-by: Automatic_Commit_Validation_User
|
|
Enable SDR104 and SDR50 support for Tegra3.
Bug 920089
Bug 913598
Reviewed-on: http://git-master/r/75248
Change-Id: Ib7e7d15f1a42a14bb1ecb3e0f25934309ec43534
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78022
Reviewed-by: Automatic_Commit_Validation_User
|
|
Adding option for non std freq tuning for
host controllers that have deviation in the
tuning procedure.
Bug 920089
Change-Id: I8ca6962c6f0380c1160460e5094c47aee241d6e3
Reviewed-on: http://git-master/r/72603
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I97cceb39fd27b159823ebce6706c5e74e53deccd
Reviewed-on: http://git-master/r/77303
Reviewed-by: Automatic_Commit_Validation_User
|
|
If PADPIPE_CLKEN_OVERRIDE is not set, CMD end bit
errors are observed due to timing issues on some
micro SD UHS cards.
Bug 921412
Bug 914182
Bug 905519
Change-Id: Ie926843010e3082bf3469913c1f2ced0bfb008d2
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/74315
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/75150
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
|
|
commit 3b6e3c73851a9a4b0e6ed9d378206341dd65e8a5 upstream.
When getting a cmd irq during an ongoing data transfer
with dma, the dma job were never terminated. This is now
corrected.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Per Forlin <per.forlin@stericsson.com>
Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Change-Id: Id2b0cc97b7da31bb0e2bad0653bc387dbe760134
Reviewed-on: http://git-master/r/74196
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
|
|
commit b63038d6f4ca5d1849ce01d9fc5bb9cb426dec73 upstream.
The interrupt was previously enabled and then correctly cleared.
Now we also handle it correctly.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Change-Id: I62f75a5704eb27b1e67d28235f6aa6a8d3798662
Reviewed-on: http://git-master/r/74195
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
|