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This fixes PCIe EP device self-initialisation in case only a regular
reset EP GPIO is used as PERST# which is e.g. the case on our Ixora
carrier board by always waiting 20 milliseconds after releasing PERST#.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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If the reset gpio for a PCIe switch is invalid, but a gpio for
reseting downstream EP devices is valid no reset pulse for the EP devices is
generated.
(i.e. in the device tree reset-gpio is not defined but reset-ep-gpio is defined)
The patch fixes this.
Original patch from Juha Kokkonen, Huoltamoeletroniikka Ky
(cherry picked from commit f593ebc9921013a992c1d096bf4cbad17c1af01b)
Conflicts:
drivers/pci/host/pci-imx6.c
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With the following dtb node one can define a gpio to reset
downstream endpoints.
reset-ep-gpio = <...>;
Currently the logic is 1 for reset asserted
and 0 for reset deasserted.
Some pcie switches require their downstream endpoints to be kept in reset
for an additonal millisecond after their reset has been deasserted.
(cherry picked from commit 94a60e7f645965b1e422e4e80aa8ccb9e0ec845c)
Conflicts:
drivers/pci/host/pci-imx6.c
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Conflicts:
drivers/pci/host/Kconfig
drivers/pci/host/pci-imx6.c
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imx pcie used the wrab mode to do the cached access
methods on axi bus. There is 64bytes address mis-aligned
problem.
Disable the cached operations.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit 85db70336ab66136481926bcd7f5abe599e2aa4f)
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Regarding to the lpsr mode on imx7d arm2 board
- turn off/on imx7d pcie phy during suspend/resume
- add the pcie ep power on/off control
- align the imx6sx/imx7d pcie pm operations.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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some pcie pe devices maybe still failed resime back,
after pcie rc is resumed, when the pcie ep devices have
a heavy loading task.
Enlarge the delay time after imx6qp pcie rc resume back.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platforms
Enalbe the msi pcie ep rc on it.
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@imx6sxsabresd:~# ./memtool -32 <msi_addr>=0
Writing 32-bit value 0x0 to address <msi_addr>
- RC side(console command and kernel message):
root@imx6sxsabresd:~# cat /proc/interrupts | grep MSI
384: 1 PCI-MSI
Note:
imx6q msi_addr 0x01ff_8000
imx6sx msi_addr 0x08ff_8000
imx7d msi_addr 0x4ffc_0000
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platforms
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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There is w_disable signal design on the pcie interface
on imx7d sdb board.
Add the w_disable control into imx pci driver, and
initialized it to be high
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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phenomena:
There is no such kind of phenomen when the "no_consol_suspend"
is added into kernel cmd line.
But there maybe kernel dump when the "no_consol_suspend" is
removed from kernel cmd line.
Root cause:
After the RC resume back and link is up, delay for a while is
required to let ep to resume from D3 mode
Regarding to RM DOC, no status bit can be used to make a
check on it, thus a while delay had been added.
Test results: Over weekend stress tests are passed.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
(cherry picked from commit 1046f1eb20979cdd874d99601ee889ddf26caf51)
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As busfreq head file name is changed from busfreq-imx6.h
to busfreq-imx.h, change the drivers which include this
head file accordingly.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- add the perst for imx pcie because that this signal
is mandatory required to be asserted/de-asserted
during suspend/resume.
Otherwise, pcie ep maybe failed to resume back.
- for imx7 pcie
- use the external osc, otherwise the internal pll
- adjust the ltssm de-assert
- change the init of pcie to late_initcall, because
the expansion spi gpio is used as pcie_rst_b and
pcie_dis_b on imx7d/imx6qp boards, and pcie driver has
to be loaded after spi/i2c driver is probed.
- cansleep set value function should be used to
manipulate the expansion gpios.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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add the pm mechanism for imx6qp pcie
- enlarge the delay after pme_turn_off is set, then l23
can be enterred.
- HW rework to use the dedicated gpio pin(gpio1_14) as
the perst and change the sequence of the perst.
- use the recommended deemp and swing configurations.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- enable pcie functions on imx7d platforms
- grst/brst should be asserted/de-asserted during resume, since
the pcie phy power would be cut off automatically by HW during
system suspend/resume
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Do not switch the mem view when the imx pcie ep/rc
validation system is enabled.
Otherwise, the RC wouldn't access the mem of the ep
device in the imx pcie ep/rc validation system.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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disp_mix power domain is mandatory requried by imx6sx
pcie. Add the related operations for imx6sx pcie
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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enable imx6qdl pcie on imx_3.14 kernel
and add the pcie pm workaround for imx6qdl.
------
L2 can exit by 'reset' or Inband beacon (from remote EP)
toggling phy_powerdown has same effect as 'inband beacon'
So, toggle bit18 of GPR1, used as a workaround of errata
"PCIe PCIe does not support L2 Power Down"
WARNING: This is not official workaround for ERR005723.
Fortunately, we don't encounter issue with this workaround.
User should take own risk to use it.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- Regarding to the pcie design on imx6sx, some gpc
operations are mandatory pre-required when pcie phy
is powered on/off.
In order to DO NOT touch gpc module in pcie driver,
register one pcie phy regulator into gpc, encapsulate
the pcie phy power on/off pre gpc related operations into
regulator's notify and contained in gpc driver
- in order to save power consumption, disable pcie clks and phy
regulator if the pcie link is down.
- remove the PRST set/unset in suspend/resume, because that
usb hub would be reset, and the name of the dev node of the
thumb disk inserted in the port of the pcie2usb device,
would be changed randomly after suspend resume on imx6sx.
- add the extremely power save mode
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system
- in order to avoid the modification of common codes,
force the msi address to be fixed.
(imx6sx:0x08ff8000, imx6q/dl:0x01ff8000)
Test howto on imx6sx:
(Replace the 08ff8000 by 01ff800 when imx6q/dl are used.)
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@imx6sxsabresd:~# ./memtool -32 08ff8000=0
Writing 32-bit value 0x0 to address 0x08FF8000
- RC side(console command and kernel message):
root@imx6sxsabresd:~# cat /proc/interrupts | grep MSI
384: 1 PCI-MSI
Signed-off-by: Richard Zhu <r65037@freescale.com>
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hw setup:
* two imx6q sd (imx6sx sdb) boards, one is used as pcie rc,
the other is used as pcie ep. Connected by fsl pcie adap
adaptors.
sw setup:
* when build rc image, make sure that
CONFIG_IMX_PCIE=y
# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
CONFIG_RC_MODE_IN_EP_RC_SYS=y
* when build ep image
CONFIG_EP_MODE_IN_EP_RC_SYS=y
# CONFIG_RC_MODE_IN_EP_RC_SYS is not set
features:
* set-up link between rc and ep by their stand-alone
ref clk running internally.
* in ep's system, ep can access the reserved ddr memory
(default address:0x4000_0000 on imx6q sd board, and
0xb000_0000 on imx6sx sdb board) of pcie rc's system, by the
interconnection between pcie ep and pcie rc.
* add the configuration methods in the ep side, used to
configure the start address and the size of the reserved
rc's memory window.
- cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
- echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
- echo 0x800000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set
* provide one example, howto configure the bar# and so on,
when pcie ep emaluates one memory ram ep device
* setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
on imx6q sd board, and 0xb000_0000 on imx6sx sdb board.
NOTE:
* boot up ep platform firstly, then boot up rc platform.
* make sure that mem=768M is contained in the kernel command line,
since the start address of the upper 256mb of the 1g ddr mem is
reserved to do the pcie ep rc access operations in default.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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- imx6sx pcie has its own standalone pcie power supply.
In order to turn on the imx6sx pcie power during
initialization. Add the pcie regulator and the gpc regmap
into the imx6sx pcie structure.
- imx6sx pcie has the new added reset mechanism, add the
reset operations into the initialization.
- register one PM call-back, enter/exit L2 state during
system suspend/resume.
use noirq pm_ops instead of the general pm_ops in dev_pm_ops,
since cfg read/write may occurs after suspend and before resume.
do msi store/re-store in suspend/resume callbacks, since
controller maybe turned off, and these msi cfg maybe lost
in suspend.
- disp_axi clock is required by pcie inbound axi port actually.
Add one more clock named pcie_inbound_axi for imx6sx pcie.
- host init maybe failed, return negative value when
there is a failure in the host init.
- assert per-reset in suspend, and de-assert it in resume.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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For boards without a reset gpio we skip the delay between enabling
the pcie_ref_clk and touching the RC registers for configuration.
System would be hangs when the clocks are not yet settled in the DW
PCIe core. So we need to make sure that there is always an
appropriate delay between those two actions.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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if va_cfg0_base/va_cfg1_base are initialized by
designware core, the pp->cfg.start is not initialized
properly, when IORESOURCE_MEM "config" is represented
as cfg space resource.
solution: assign cfg_res->start to pp->cfg.start.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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host init maybe failed, change the func type of host_init
defined in struct pci_host_ops from void to int.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one store/re-store msi cfg functions. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
these functions can be used to store/restore the msi data
and msi_enable during the suspend/resume callback.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
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According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.
Delay enabling the reference clock for the SS function until it has
stabilized. This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.
[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
(cherry picked from commit 3fce0e882f61513c45c67e15bd0fde03341b58a5)
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This effectively reverts f216f57ffe6e ("PCI: imx6: Probe the PCIe in
fs_initcall()") as the resource allocation issue that prevented the driver
from working properly at module_initcall level is now fixed in
pcie-designware.c.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 61da50da903fdfc00b40f3b3e3abeca7ae51b591)
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dw_pcie_host_init()
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
(cherry picked from commit 8ddebc4103e6544bd31f0c97e55491387717a124)
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Use pci_create_root_bus() similar to other PCI host controller drivers.
The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus. This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.
To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered. Switching to pci_create_root_bus() allows us to get rid of
this special handling.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
(cherry picked from commit 92483df2bad7649caacad60ec7b0f8016e894e11)
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This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
(cherry picked from commit 4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6)
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This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use. The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.
According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do. Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.
As a workaround, force LTSSM into detect state right before hitting the
disable switch. There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.
[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
(cherry picked from commit 3e3e406e3807235906ee0b7c697664ea6dfd88de)
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The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.
1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.
2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.
3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
(cherry picked from commit b14a3d1784a9252aa3bbe0bb9d14588be32f18a1)
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DesignWare v3.65 hardware implements MSI controller registers in
application space. This requires updates to the DesignWare core to
support controllers based on this older hardware.
Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
in the application register. Also, v3.65 hardware uses the MSI_IRQ
register in application register space to raise MSI IRQ to the RC from EP.
Current code uses the standard mechanism as per PCI spec. So add
get_msi_data() to get the address of this register so common code can
work on both v3.65 and newer hardware.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
(cherry picked from commit 2f37c5a81cff2c341fa19fdd132ece6aea30a735)
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DesignWare v3.65 hardware requires application space registers to be
configured to access the remote EP config space.
To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
(cherry picked from commit a1c0ae9c24627a12c781ebd9947a6442861f6168)
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Add support for PCIe controller in DRA7xx. This driver re-uses the
designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 47ff3de911a728cdf9ecc6ad777131902cff62b4)
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In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit f4c55c5a3f7f68c06cc559ed7af8b2d017cbb0a7)
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The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address space
in the designware driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 4dd964df36d0e548e1806ec2ec275b62d4dc46e8)
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mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
ARCH_MVEBU is sufficient.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
(cherry picked from commit c27602086d08d22b067a1267e09fb32b4b096aa0)
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ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.
Adds bindings for this new driver and update MAINTAINERS as well.
Cc: linux-pci@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
(cherry picked from commit 51b66a6ce12570e5ee1a249c811f7f2d74814a43)
Conflicts:
MAINTAINERS
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Add support for a generic PCI host controller, such as a
firmware-initialised device with static windows or an emulation by
something such as kvmtool.
The controller itself has no configuration registers and has its address
spaces described entirely by the device-tree (using the bindings from
ePAPR). Both CAM and ECAM are supported for Config Space accesses.
Add corresponding documentation for the DT binding.
[bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
(cherry picked from commit ce292991d88b77160f348fb8a3a2cf6e78f4b456)
Conflicts:
drivers/pci/host/Kconfig
drivers/pci/host/Makefile
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This patch adds support for Message Signaled Interrupts in the imx6-pcie
driver.
Signed-off-by: Harro Haan <hrhaan@gmail.com>
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit d1dc9749a5b8239d9ae718a176b5cd39ff89f976)
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On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make
sure we don't bail too early from the IRQ handler.
The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 7f4f16eef5aeba31bdfb7702ced06a42f2777e04)
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They are dropped with the new binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 5c40eea7783bbcdd5795cd7d50b7b3fd9a94dc94)
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We don't need this anymore. The IRQs are now properly mapped through the
DT.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit e521519a84f6d796d3cff756969cd5902c9550dd)
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As defined in the new binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 57526136532408bacf2f68c26027abc2924b45d1)
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imx6_add_pcie_port() is called only from from imx6_pcie_probe() which is
annotated with __init. Thus it makes sense to annotate
imx6_add_pcie_port() with __init to avoid section mismatch warnings.
[bhelgaas: changelog]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Sean Cross <xobs@kosagi.com>
(cherry picked from commit 44cb5e94f96cef72a977fc5fdea8095bc0ae25ba)
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add_pcie_port() is called only from exynos_pcie_probe(), which is annotated
with __init. Thus it makes sense to annotate add_pcie_port() with __init
to avoid the following section mismatch warning:
WARNING: drivers/pci/built-in.o(.text.unlikely+0xf8): Section mismatch in reference from the function add_pcie_port() to the function .init.text:dw_pcie_host_init()
The function add_pcie_port() references
the function __init dw_pcie_host_init().
This is often because add_pcie_port lacks a __init
annotation or the annotation of dw_pcie_host_init is wrong.
[bhelgaas: changelog]
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
(cherry picked from commit 17d7acc8e1c81f8125730aa900c67412a2ac69e2)
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