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If pin is configured on gpio mode and set for input direction
then set e_input = 1 and if pin is set for output direction
then set tristate = 0 for that pin.
Bug 200033491
Change-Id: Ibcae17ad8bf4e45f0c74eb68d3bf975078fb67d6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/416650
(cherry picked from commit 3dbac8e8382be0766e221c3f47f6254538b17030)
Reviewed-on: http://git-master/r/498327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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For Tegra124, all drive groups does not supports all
configuration. The configuration which is not supported
is having the bits as -ve in their pinconfig table but
related variable is declared as unsigned making this
configuration as valid.
Correct the datatype of the drive groups configuration bits
and handling this properly across the driver to ignore the
configuration which is not supported.
Change-Id: I9b5666f7fa966df05df566196d155b516cded629
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/361999
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Correct the pincontrol driver group name of Tegra114 and Tegra124 on
soc specific initialisation table.
Change-Id: I3af8028aae3edfaade727a41f8c7c94ca4e859f2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/329990
GVS: Gerrit_Virtual_Submit
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Every soc have their default driver configuration based on
characterization recommendation.
Add support to configure the drive group during pincontrol
driver initialisation.
Change-Id: I9af34c65feb77a5bb8af15a08dffe246e8c8eb9d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/327754
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Change-Id: I511f1013be0b5625733a81eb1dfd2deb822909db
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/327062
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
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The non-dt mux option is defined in the mach/pinmux.h and hence
added these option in the pingroup table to look for non-dt mux option
when using the driver from board files.
Change-Id: Ic0c04513f4ebdc0ce8abab06f373518a6dc14dd5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/326724
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
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drive-type is not supported for pinctrl-tegra20 and pinctrl-tegra30
so set drvtype_reg to -1 for them.
Bug 1003210
Change-Id: I330fb8049a3e3d6f905e385aedb782d06f1ca002
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/167754
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH
Bug 1052024
Reviewed-on: http://git-master/r/134325
(cherry picked from commit 572bb757c9c7d867b92531d2fb8428f819e2a586)
Change-Id: I164311ddcf16dea31df9c04a0c33ca08537b5d22
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/147530
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R4e5f91ba548172c1a1e7af3bfd74aad77b15fb31
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This reverts commit 3b2f9412962d2baaa8bf8297103c2ae46b6f929d.
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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This reverts commit 348d1bf75c09f854630e9bd161dc2a88aebe2149.
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.
rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH
drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0
Add support of these parameters to be configure from DTS file.
Tegra20 and Tegra30 does not support this configuration and hence initialize their
pinmux structure with reg = -1.
Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Now that Tegra's pinmux is configured solely from device tree, there's
no need for the pinconf types to be defined in arch/arm/mach-tegra/.
Move it into the pinctrl directory to clean up mach-tegra, as a pre-
requisite for single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Rather than having a single tegra-pinctrl driver that determines whether
it's running on Tegra20 or Tegra30, instead have separate drivers for
each that call into utility functions to implement the majority of the
driver. This change is based on review feedback of the SPEAr pinctrl
driver, which had originally copied to Tegra driver structure.
This requires that the two drivers have unique names. Update a couple
spots in arch/arm/mach-tegra for the name change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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This adds a driver for the Tegra pinmux, and required parameterization
data for Tegra20 and Tegra30.
The driver is initially added with driver name and device tree compatible
value that won't cause this driver to be used. A later change will switch
the pinctrl driver to use the correct values, switch the old pinmux
driver to be disabled, and update all code that uses the old pinmux APIs
to use the new pinctrl APIs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
[squashed "fix case of Tegra30's foo_groups[] arrays"]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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