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2013-04-09pinctrl: exynos5440: fix probe failure due to missing pin-list in config nodesThomas Abraham
The property 'samsung,exynos5440-pins' is optional in configuration nodes which are included in the Exynos5440 pin-controller device node. Fix the incorrect failure in driver probe if 'samsung,exynos5440-pins' property is not found in the configuration nodes. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: ab8505: Staticize some symbolsSachin Kamat
Silences the following warnings: drivers/pinctrl/pinctrl-ab8505.c:274:28: warning: symbol 'ab8505_alternate_functions' was not declared. Should it be static? drivers/pinctrl/pinctrl-ab8505.c:351:32: warning: symbol 'ab8505_gpio_irq_cluster' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: ab8540: Staticize some symbolsSachin Kamat
Silences the following warnings: drivers/pinctrl/pinctrl-ab8540.c:302:28: warning: symbol 'ab8540_alternate_functions' was not declared. Should it be static? drivers/pinctrl/pinctrl-ab8540.c:379:32: warning: symbol 'ab8540_gpio_irq_cluster' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: ab9540: Staticize some symbolsSachin Kamat
Fixes the following warnings: drivers/pinctrl/pinctrl-ab9540.c:382:28: warning: symbol 'ab9540alternate_functions' was not declared. Should it be static? drivers/pinctrl/pinctrl-ab9540.c:457:32: warning: symbol 'ab9540_gpio_irq_cluster' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: ab8500: Staticize some symbolsSachin Kamat
These symbols are used only in this file. Silences the following warnings: drivers/pinctrl/pinctrl-ab8500.c:392:28: warning: symbol 'ab8500_alternate_functions' was not declared. Should it be static? drivers/pinctrl/pinctrl-ab8500.c:458:32: warning: symbol 'ab8500_gpio_irq_cluster' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: abx500: Staticize some symbolsSachin Kamat
These symbols are used only in this file. Without this patch we get the following warnings: drivers/pinctrl/pinctrl-abx500.c:520:5: warning: symbol 'abx500_gpio_request' was not declared. Should it be static? drivers/pinctrl/pinctrl-abx500.c:527:6: warning: symbol 'abx500_gpio_free' was not declared. Should it be static? drivers/pinctrl/pinctrl-abx500.c:614:5: warning: symbol 'abx500_gpio_request_enable' was not declared. Should it be static? drivers/pinctrl/pinctrl-abx500.c:714:5: warning: symbol 'abx500_pin_config_get' was not declared. Should it be static? drivers/pinctrl/pinctrl-abx500.c:721:5: warning: symbol 'abx500_pin_config_set' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: Add pinctrl-s3c64xx driverTomasz Figa
This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: samsung: Handle banks with two configuration registersTomasz Figa
This patch adds support for banks that have more than one function configuration registers, e.g. some of the banks of S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: samsung: Remove hardcoded register offsetsTomasz Figa
This patch replaces statically hardcoded register offsets of Exynos SoCs with an array of register offsets in samsung_pin_bank_type struct. Thanks to this change, support for SoCs with other set and order of registers can be added (e.g. S3C24xx and S3C64xx). Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: samsung: Split pin bank description into two structuresTomasz Figa
This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: samsung: Include pinctrl-exynos driver data conditionallyTomasz Figa
Since pinctrl-samsung is a common part of the pin control support for several Samsung SoCs, it can be compiled without Exynos support enabled. This patch surrounds Exynos-specific driver data with ifdefs to include them only when support for Exynos is enabled. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> [Fixed up EXYNOS4->EXYNOS] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: samsung: Protect bank registers with a spinlockTomasz Figa
Certain pin control registers can be accessed from different contexts, i.e. pinctrl, gpio and irq functions. This makes the locking provided by pin control core insufficient. This patch adds necessary locking using a per bank spinlock as it was done in the old Samsung GPIO driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-08Merge tag 'omap-for-v3.10/timer-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers From Tony Lindgren <tony@atomide.com>: Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>: This series consists mainly of clean-ups for clockevents and clocksource timers on OMAP2+ devices. The most significant change in functionality comes from the 5th patch which is changing the selection of the clocksource timer for OMAP3 and AM335x devices when gptimers are used for clocksource. Note that this series depends on 7185684 (ARM: OMAP: use consistent error checking) in RMK's tree and 960cba6 (ARM: OMAP5: timer: Update the clocksource name as per clock data) in omap-for-v3.10/fixes-non-critical. So this branch is based on a merge of 7185684 and omap-for-v3.10/fixes-non-critical to avoid non-trivial merge conflicts. * tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4+: Fix sparse warning in system timers ARM: OMAP2+: Store ID of system timers in timer structure ARM: OMAP3: Update clocksource timer selection ARM: OMAP2+: Simplify system timers definitions ARM: OMAP2+: Simplify system timer clock definitions ARM: OMAP2+: Remove hard-coded test on timer ID ARM: OMAP2+: Display correct system timer name ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-08Merge branch 'gic/cleanup' into next/soc2Arnd Bergmann
Both zynq and shmobile have conflicts against the gic cleanup series, resolved here. Conflicts: arch/arm/mach-shmobile/smp-emev2.c arch/arm/mach-shmobile/smp-r8a7779.c arch/arm/mach-shmobile/smp-sh73a0.c arch/arm/mach-zynq/platsmp.c drivers/gpio/gpio-pl061.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-08Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into ↵Arnd Bergmann
next/drivers From Tony Prisk <linux@prisktech.co.nz>: arm: vt8500: Add pinctrl driver for arch-vt8500 This series adds support for the pinctrl/gpio module on all arch-vt8500 supported SoCs. As part of the review process, some tidy up is also done to drivers/of/base.c to remove some code that is being constantly duplicated. Also, a patch for the bcm2835 pinctrl driver is included to take advantage of the new of/base.c code. * tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits) pinctrl: bcm2835: make use of of_property_read_u32_index() gpio: vt8500: Remove arch-vt8500 gpio driver arm: vt8500: Remove gpio devicetree nodes arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500 arm: vt8500: Increase available GPIOs on arch-vt8500 of: Remove duplicated code for validating property and value of: Add support for reading a u32 from a multi-value property. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04pinctrl: bcm2835: make use of of_property_read_u32_index()Stephen Warren
Use the new standard API of_property_read_u32_index() instead of open- coding it. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
2013-04-04pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500Tony Prisk
This patch adds support for the GPIO/pinmux controller found on the VIA VT8500 and Wondermedia WM8xxx-series SoCs. Each pin within the controller is capable of operating as a GPIO or as an alternate function. The pins are numbered according to their control bank/bit so that if new pins are added, the existing numbering is maintained. All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and WM8850. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03Merge tag 'v3.9-rc5' into develLinus Walleij
Linux 3.9-rc5 Conflicts: drivers/pinctrl/pinconf.c
2013-04-03pinctrl/abx500: fix ab9540 alternate functionPatrice Chotard
This fix allows to correctly select default and alternate pin mode. By default for all ABx500 family chip, pin default mode is selected by clearing corresponding bit in GPIOSELx register except for pins which support alternate function, in this case, corresponding bit must be set. But, due to an unlogical hardware implementation, for one particular pin (GPIO11) reverse setting must be done. For that, update the alternate function array by declaring that this pin supports alternate function. Same issue has been fixed in pinctrl-ab8505.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl/pinconf: partial revert of pin config debugfsLinus Walleij
I accidentally left this patch: commit 6f9e41f4e673bf9ae6a5c0831b1524a91ea1c440 "pinctrl/pinconfig: add debug interface" in the tree though the patch was not yet finished. Revert it partially (we need the infrastructural changes). Cc: Laurent Meunier <laurent.meunier@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl/nomadik: add device tree bindings for db8540Gabriel Fernandez
This adds a simple device tree binding for db8540 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@stericsson.com> Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: simplify the re-enable old state code in pinctrl_select_stateRichard Genoud
Instead of just enabling the settings that were disabled in the 1st loop, it's simpler to recall pinctrl_select_state with the old state. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: select_state: don't call pinctrl_free_setting on errorRichard Genoud
As Stephen Warren pointed out, pinctrl_free_setting() was called instead of pinmux_disable_setting() on error. In this error code, we want to call pinmux_disable_setting() where pinmux_enable_setting() was called. And when pinconf_apply_setting() was called, we can't do much to undo the pin muxing (the closest thing I can think about for "unmuxing" a pin is muxing it as GPIO input). Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: coh901: Fix error checking in u300_gpio_to_irqAxel Lin
The pointer "port" is always not NULL if gpio->port_list is not empty. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: pinctrl_select_state: set the old_state back on errorRichard Genoud
In unapply_new_state, the old state is re-applied, but p->state is not set back as it should. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: remove superfluous optimization in pinctrl_select_state_lockedRichard Genoud
As Stephen Warren suggested, checking first if the setting->node entry is the first in the list or not is superfluous, as it is checked again in the list_for_each_entry bellow. So, remove it, the code will be simpler and lighter ! Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: use dev_info instead of pr_info in pinctrl_select_state_lockedRichard Genoud
And remove superfluous brackets. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: sunxi: add clock supportEmilio López
For the port controller to work, we need to enable the apb0_pio gate. This commit adds the ability to enable one clock specified on the device tree to the pinctrl driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: core: add dependence of GPIOLIBHaojian Zhuang
In file included from drivers/pinctrl/core.c:30:0: include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep': include/asm-generic/gpio.h:270:2: error: implicit declaration of function '__gpio_get_value' [-Werror=implicit-function-declaration] include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep': include/asm-generic/gpio.h:276:2: error: implicit declaration of function '__gpio_set_value' [-Werror=implicit-function-declaration] drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range': drivers/pinctrl/core.c:297:9: error: implicit declaration of function 'gpio_to_chip' [-Werror=implicit-function-declaration] drivers/pinctrl/core.c:297:27: warning: initialization makes pointer from integer without a cast [enabled by default] drivers/pinctrl/core.c:304:45: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:26: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:39: error: dereferencing pointer to incomplete type cc1: some warnings being treated as errors make[2]: *** [drivers/pinctrl/core.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make[1]: *** Waiting for unfinished jobs.... It's caused by CONFIG_GPIOLIB isn't enabled for some platform. So add the dependence on pinctrl_ready_for_gpio_range(). Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl/abx500: fix ab8505 alternate functionPatrice Chotard
This fix allows to correctly select default and alternate pin mode. By default for all ABx500 family chip, pin default mode is selected by clearing corresponding bit in GPIOSELx register except for pins which support alternate function, in this case, corresponding bit must be set. But, due to an unlogical hardware implementation, for one particular pin (GPIO11) reverse setting must be done. For that, update the alternate function array by declaring that this pin supports alternate function. Reported-by: Ramesh Chandrasekaran <ramesh.chandrasekaran@stericsson.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-02Merge tag 'renesas-boards3-for-v3.10' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2 Third round of Renesas ARM SoC board updates for v3.10 Highlights: * Add Lager board support * Add ape6evm board support * Add Bock-W board support * Mackerel MMCIF/SDHI clean ups * Add ethernet support to kzm9g-reference This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10 The merge with renesas-pinmux2-for-v3.10 was made to provide run-time dependencies for the following changes: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support * tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (307 commits) ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection ARM: shmobile: mackerel: add interrupt names for SDHI0 ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio ARM: shmobile: mackerel: remove OCR masks, where regulators are used ARM: shmobile: mackerel: SDHI resources do not have to be numbered ARM: shmobile: Initial r8a7790 Lager board support ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support ARM: shmobile: APE6EVM base support ARM: shmobile: kzm9g-reference: add ethernet support ARM: shmobile: add R-Car M1A Bock-W platform support sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-02Merge tag 'renesas-pinmux2-for-v3.10' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2 Second round of Renesas ARM and SH based SoC pinmux updates for v3.10 Highlights: * Compilation fixes for sh7269 and for when CONFIG_BUG is not set * sh-pfc Support for r8a73a4 SoC * Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 * tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits) sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support sh-pfc: r8a73a4: GPIO IRQ support sh-pfc: r8a73a4: Support sparse GPIO numbers sh-pfc: Add r8a73a4 pinmux support sh-pfc: r8a7779: Split DU input and output pixel clocks sh-pfc: r8a7779: Remove GPIO data ARM: shmobile: r8a7779: Register GPIO devices sh-pfc: Configure pins as GPIOs at request time when handled externally sh-pfc: Skip gpiochip registration when no GPIO resource is found sh-pfc: Make GPIO support optional sh-pfc: Make function GPIOs support optional ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-02Merge tag 'renesas-soc2-for-v3.10' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2 Second round of Renesas ARM SoC updates for v3.10 Some Highlights: * Add r8a7790 SoC * Add r8a73a4 SoC * Migrate r8a7740 SoC from INTC to GIC * Add thermal driver support to r8a73a4 SoC * Add irqpin DT nodes to sh73a0 SoC * Add SCIF support to r8a7778 SoC This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-intc-external-irq2-for-v3.10 * tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits) ARM: shmobile: r8a7790 SoC 64-bit DT support ARM: shmobile: r8a73a4 SoC 64-bit DT support ARM: shmobile: r8a7790 PFC support ARM: shmobile: r8a7790 IRQC support ARM: shmobile: r8a7790 SCIF support ARM: shmobile: Initial r8a7790 SoC support ARM: shmobile: r8a7779: move global functions to r8a7779.h ARM: shmobile: r8a7740: move global functions to r8a7740.h ARM: shmobile: sh73a0: move global functions to sh73a0.h ARM: shmobile: sh7372: move global functions to sh7372.h ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock ARM: shmobile: r8a7740: use fixed ratio clock ARM: shmobile: r8a7740: tidyup comment/implementation mismatch ARM: shmobile: sh73a0: use fixed ratio clock ARM: shmobile: sh7372: use fixed ratio clock ARM: shmobile: add struct clk_ratio and fixed ratio clock macro ARM: shmobile: sh7372: remove DIV4_ZT* clocks ARM: shmobile: sh73a0: remove DIV4_ZT* clocks ARM: shmobile: sh73a0: add a TWD clock ARM: shmobile: r8a7740: Migrate from INTC to GIC ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-03sh-pfc: r8a73a4: Remove unused GPIO bias dataMagnus Damm
Remove unused pull-up/down data from the r8a73a4 PFC code. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Remove function GPIOsMagnus Damm
All r8a73a4 platforms use the pinctrl API to control pin functions. Function GPIOs are no longer needed. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Remove IRQC function GPIOSMagnus Damm
The r8a73a4 board support will use the pinctrl API to control the external IRQ pins so remove the unused function GPIOS. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Remove SCIF function GPIOSMagnus Damm
The r8a73a4 board support will use the pinctrl API to control the SCIF pins, remove the corresponding unused function GPIOS. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Add IRQC pin groups and functionsMagnus Damm
V2 of PINCTRL support for r8a73a4 IRQC hardware and in particular the external pins IRQ0 -> IRQ57. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Add SCIF pin groups and functionsMagnus Damm
Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and SCIFB0->SCIFB3. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf supportMagnus Damm
Implement pull-up/down support for r8a73a4 similar to the implementation for sh73a0. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: GPIO IRQ supportMagnus Damm
V2 of code to add GPIO -> IRQ mappings to the PFC table for the r8a73a4 SoC. Requires the IRQs to be mapped at a fixed location in Linux IRQ space. The actual IRQs are not handled by the PFC, instead IRQC is used on r8a73a4. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a73a4: Support sparse GPIO numbersMagnus Damm
The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers in the PFC SoC data. Pin numbers shall be used with the GPIO API from this point on. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: Add r8a73a4 pinmux supportMagnus Damm
Add initial PFC support for the r8a73a4 SoC. At this point only GPIO interface is supported, move to newer interfaces planned as incremental changes. Original authors are Morimoto-san with help from Yoshii-san, thanks to them for the heavy lifting. Adjusted by Magnus to work together with updated code in drivers/pinctrl. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com> Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a7779: Split DU input and output pixel clocksLaurent Pinchart
The output pixel clocks can be used without the input pixel clocks. Split them in different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: r8a7779: Remove GPIO dataLaurent Pinchart
GPIOs are now handled by a separate driver, remove GPIO data from the SoC information structure. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: Configure pins as GPIOs at request time when handled externallyLaurent Pinchart
When a GPIO is handled by a separate driver the pinmux gpio_set_direction() handler won't be called. The pin mux type then need to be configured to GPIO at request time. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: Skip gpiochip registration when no GPIO resource is foundLaurent Pinchart
Boards/platforms that register dedicated GPIO devices will not supply a memory resource for GPIOs. Try to locate the GPIO memory resource at initialization time, and skip registration of the gpiochip if the resource can't be found. This is a temporary modification to ease the transition to separate GPIO drivers. It should be reverted when all boards and platforms will have been moved. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: Make GPIO support optionalLaurent Pinchart
When implemented as a separate IP block, GPIOs should be handled by a separate driver. To make this possible GPIO support needs to be optional in the sh-pfc driver. If no GPIO data registers are supplied in the SoC information structure skip registration of the gpiochip. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03sh-pfc: Make function GPIOs support optionalLaurent Pinchart
The target is to get rid of function GPIOs completely. To reach this, make function GPIOs support optional by skipping the function GPIO chip registration if no function GPIOS are defined in SoC data. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-02sh-pfc: r8a7779: Don't use GPIO enum entriesLaurent Pinchart
Refactor the GPIO macro magic to use GPIO numbers directly instead of the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum entries from the mach/r8a7779.h header. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 10:33:14 +0000