Age | Commit message (Collapse) | Author |
|
TPS80031 supports the three external regulator named
as REGEN1, REGEN2 and SYSEN.
Supports these regulator through regulator driver.
Change-Id: I6c22aab13499a66ab8b4c68e8a5833553222decd
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/119977
|
|
Converting tps80031 regulator driver to be register as mfd
sub device of the tps65910 and register all its regulators from
single probe calls.
Add separate platform data for the regulator to be supply from
board as part of tps80031 platform data.
Change-Id: Ie65b25f3058202070f7f917e64a4a660dd941210
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/119976
|
|
Currently the platform specific data is sharing with
device information structure and hence it restrict to
use the multiple instance of the device.
Separating the device specific information to the platform
specific data and allocating different memory for
storing platform specific data.
Change-Id: I74284514c764f1ceb84f5d9dda215fea7f3cbd13
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/119975
|
|
The platform data of tps80031 have the regualtor_init_data as
non-pointer type. Converting this as pointer type for aligning
to regulator driver policy and easy support for DT.
Change-Id: I07f574953b09e0ed9ec3735d0ee7999ca35bee61
Reviewed-on: http://git-master/r/119974
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Renaming the regulator name from TPS80031_ID_* to
TPS80031_REGULATOR_* for better readability.
Change-Id: I627b6ddb78a60e44da2a869c0d51dd84166302ed
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/119972
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
This reverts commit 70e40e9cf025c73fde46d1a5577547dc37182a64
Change-Id: Iaf390c0d3ea16686f619f321bceea572ee7434fc
Reviewed-on: http://git-master/r/119802
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
This reverts commit 5bc340e408aa3f009651735c71f3c97676fbe79f
Change-Id: I70e40e9cf025c73fde46d1a5577547dc37182a64
Reviewed-on: http://git-master/r/119800
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
|
|
Renaming the regulator name from TPS80031_ID_* to
TPS80031_REGULATOR_* for better readability.
Change-Id: I6176cb213d23e44061549fd1e81306756a324523
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Adjust the tolerance voltage only when requested minimum voltage is
more than the rail's minimum voltage.
bug 997415
Change-Id: Ie139c657f8550adba07b74a0cd5d69e2b53d62c2
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/116405
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Sometimes the system allow to run in less than requested
minimum voltage and if this tolerance allow the regulator
to set voltage in lower side range than this saves the power.
For the example, if client request vmin = 975mV for regulator
voltage then it sets the voltage to 987.5mv as the nearest to this
desired value. The next lower side for the voltage is 974.8mv.
So if system runs on tolerance of 1mv and if it request for
975mv then driver can look for minimum voltage as 975 - tolerance(1)
= 974mv and possible configure 974.8mv rather than 987.5mV and so
it can save the power equivalent to 12.5mV higher voltage.
Support the configuration of tolerance value.
Change-Id: Ic8312bb397c2615a3ee0f84072ec394e513525ea
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/110523
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
|
|
Allow to configure the rail into sleep-off mode even if
the external req is not supported for a regulator.
bug 979143
Change-Id: I3c1bd789410b557a2ffc3133ca15ec3753ed2004
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/110881
Reviewed-by: Automatic_Commit_Validation_User
|
|
Fixing the voltage selection logics for a given mininum/maximum
range.
bug 934544
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/78970
(cherry picked from commit 59b0264b6eda9f1e8123ee5cd82eae7104c3513e)
Change-Id: Ib9f6e8b1b1f0603aeb02af8345704110cd87b51a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/79512
Reviewed-by: Automatic_Commit_Validation_User
|
|
The correct voltage conversion formula for the register programming
is
Code=((Vout-0.6077)/0.01266)+1
Changing existing formula to above equation.
bug 915859
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Id745cc82269282318cc064f25e789837dc0dfa7a
Reviewed-on: http://git-master/r/72017
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
|
|
Set selector also in __tps80031_ldo_set_voltage().
Bug 886170
Change-Id: I17dab9cdfa6397dbdf9dba0232e4f8de0cf364f0
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/62147
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
|
|
Supporting the sleep configuration through platform data.
Rearranging clock initialization to take external power control.
Reviewed-on: http://git-master/r/67076
(cherry picked from commit 9da9d369bdbe988b98eec9b63085dfdb26de8237)
Change-Id: I40c5a8608522dbc322e148b5d569e8f5a00faa21
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/67331
|
|
Some of the values are not supported in the LDO2 configuration
when using in track mode due to hw issue in tps80031 and
tps80032-ES1.0.
Adding proper check before configuring the LDO2 in this case.
bug 898613
Reviewed-on: http://git-master/r/65441
(cherry picked from commit 58e3672102825b662ea904b46b6c1efbf639365b)
Change-Id: I4e63a932d32c7cb2d13a07611acfa0b7dae649cc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/66327
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R8b818dcb4fdaab118426df32144f846a0ab00fb3
|
|
Moving the configuration function for configuring the
rail control through the PREQ line to core from regulator
driver.
Fixing the correct voltage configuration for the LDO2 based
on TRACK mode.
Reviewed-on: http://git-master/r/63503
(cherry picked from commit 9190130f6cf1ba0bae3231321841ebe4ad94a54e)
Change-Id: I7dd511da7f809a44b1e66706054c0a4c57c36323
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/64055
Rebase-Id: R433728b4c83ccaf6f3ae2734412a90d9c89b6a2c
|
|
When any rail is configured such that it can be enable by PREQ1
then only control the sleep mode of rails through TRANS register,
not the STATE register.
PREQ1 control the rail to switch from active to sleep and
sleep to active mode.
Reviewed-on: http://git-master/r/58278
(cherry picked from commit 6a8db3200c3119673b85769b1caa56422a22b4f9)
Change-Id: I9763a4d283f0171eb9b7755d44ca3b9059755033
Reviewed-on: http://git-master/r/59289
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R25d191b2429a5f60e77d70aed1eefecaa3b75ba3
|
|
Current regulator_ops interface expects selector value to be returned.
Not doing so results in uninitialized variables used.
Bug 886170
Change-Id: I23e664790311e434303eb23fafd194502ae2909c
Reviewed-on: http://git-master/r/56654
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R72759360aeca354ef82d0ec7431e8c9f2fcafdfb
|
|
Using the register caching for optimizing the update of pmu register
through i2c. In this way, the frequent read of pmu register is
avoided.
bug 870689
Reviewed-on: http://git-master/r/56617
(cherry picked from commit 59426b56710e06b075769b4eb73723c3dcf28710)
Change-Id: I9fc339587c8c5c82443bb99489992d608fd3534e
Reviewed-on: http://git-master/r/56872
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: Reb0312eaaa88f9b082c540b752663089964ffee8
|
|
Adding support for delay configuration after setting the voltage
from platform data based on board behavior.
Also providing flag to enable the VBUS discharging though internal
pull down.
bug 853393
Change-Id: I27e7ae1eab9893241e775e17ec7b98afac71195b
Reviewed-on: http://git-master/r/41886
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R395c7ac35ccfabbea8de403d0db3cc4708981ab8
|
|
The LDOs are supporting 1.0V to 3.3V on TPS80031, but current
driver was implemented 1.1V to 3.3V. So corrected this.
And adding bit mask in ldo_get_voltage to prevent wrong voltage calculation.
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Original-Change-Id: Ic3779730fd8ad1dec6cf156b4582b0099734e7e6
Reviewed-on: http://git-master/r/39515
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rffc735384a266c5d8cde7697e25d9d3f3081597c
|
|
Original-Change-Id: I0bcfd38569b9a9a1cc21d0e9d12a0d114d87be9c
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rf1f1609942bd3ca4fae07ab37304cb214ab87774
|
|
The state register is read and write register, if read, it returned
current state, not current written value in register.
So if it want to write the value into state register, it must unconditional
write the value, don't use update(read and compare and then write).
Bug 838189
Original-Change-Id: I2555875a822f159e664b0834af2d00073c859acd
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/38396
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Ra90d4ccbe0373bbdad44422e8ff6798eea96019a
|
|
Based on platform, it is require to control the regulator
output through the peripheral power request signal to pmu.
Supporting this type of platform configuration to control
output voltage by sw as well as through PREQ input line.
bug 839809
bug 829405
Original-Change-Id: Ifa19b9062ca2a2c5cae84de1f311a33cec094ad0
Reviewed-on: http://git-master/r/38936
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R396800524fcea5c74711aec305c29229d32a0908
|
|
Providing the control of VBUS through regulator api.
bug 833736
Original-Change-Id: Id79f64dfb0ab30a5f0663521defb60a76681c767
Reviewed-on: http://git-master/r/38499
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Rebase-Id: R218327eaf38a09215ca2fe4f6e7e90c8e961d21f
|
|
This change adds the possibility of addressing all addresses on the
tps80031 I2C Bus. The interrupt registers and SMPS1/2 and VIO require
using different I2C addresses to be reached correctly.
bug 830904
Original-Change-Id: I1b5b0d03e531c3c8a0551e5049055930e742e10f
Reviewed-on: http://git-master/r/34866
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rd3ec6b9b3fac3c13e0b6a58af428110e7e51a2c8
|
|
Adding core and regulator driver for the TI pmu device tps80031.
Following functionality is added:
- Basic core driver interface to access register.
- Regulator driver.
- gpio driver.
- interrupt support from pmu.
- clock 32 initialization.
bug 830904
bug 829658
Original-Change-Id: I41e732c0b5d0472209798552b5264038e5a97ee4
Reviewed-on: http://git-master/r/33109
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R72919d00e28138767da61d673c9e805f74911341
|