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1. SRTC used loop to check WPLP status bits in order to ensure the
completion of write operations. However there is the possibility that
software is pending on loop if WPLP status bit is not updated well.
So it's safter to change the codes to wait about 3 CKIL cycles.
2. Use udelay in initialization state
Signed-off-by: Lily Zhang <r58066@freescale.com>
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disable RTC clock when it's not active
Signed-off-by: Lily Zhang <r58066@freescale.com>
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System stops at WPLP bit waiting check when using hwclock function
built with util-linux. To avoid this kind of unstable writing failure,
wait for some cycles to ensure the write operation to LP is done before
doing another LP write operation
Signed-off-by: Lily Zhang <r58066@freescale.com>
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1. Keep VSRTC and CLK32KMCU on for all states for MC13892
2. Even if low security mode, allow SRTC move to valid state except MX51 TO1.
3. When main battery is removed, coincell battery on MX51/MX37 MC13892
board is used. Please ensure the voltage of coincell battery is enough
to keep VSRTC alive.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Port rel_imx_2.6.26_3.3.0 to 2.6.28.
PMIC Regulator and ASoC drivers are removed and not yet ported.
Updated asm/arch headers for move to plat-mxc/include/mach
device_create parameters changed.
sysdev attribute functions changed.
Adopt mainline MX3 timer code and update clock init flow.
Signed-off-by: Rob Herring <r.herring@freescale.com>
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