Age | Commit message (Collapse) | Author |
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Set default videomode happens during probe and resume. _tegra_dc_enable
is also called during hotplug, setting default videomode there causes
hdcp test failure. Also, fixes checkpatch.pl errors.
bug 991805
Change-Id: Ica3cab9dd96d9766bd63301000ec29edc510ee34
Reviewed-on: http://git-master/r/109362
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Marvin Zhang <mzhang@nvidia.com>
Tested-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
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bug 991805
This reverts commit 64655badec17cea1c3ad43a5fff4ed92ad862aed.
Change-Id: Ic9b4b97953f7452e32e91eae930f631b5d5444af
Reviewed-on: http://git-master/r/109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
Tested-by: Ryan Wong <ryanw@nvidia.com>
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commit 64655badec17cea1c3ad43a5fff4ed92ad862aed ( http://git-master/r/108724 )
added extra dc enable which increases ref count hence device fails to enter
into suspend. This change removes un-necessary code.
bug 1001244
Change-Id: Ib417ebbfadfb9ea8ee14d4c5163d97d580341769
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/109526
Reviewed-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This reverts commit dfd813141283891e397d73958aabad38eddfe350.
It causes HDMI HDCP test to fail.
bug 991805
Conflicts:
drivers/video/tegra/dc/dc.c
Change-Id: I6c5d9049a2bd53b12b6da9f8578f9e2e901f8f9a
Reviewed-on: http://git-master/r/108724
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Marvin Zhang <mzhang@nvidia.com>
Tested-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
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Detect the stride size used by the bootloader.
If DC is not enabled, fallback to a default stride size.
Bug 973111
Change-Id: If04647ddf04a44987cd841062ff30e03fa4d6a02
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/104031
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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- currently, function pointers are inside nvhost_device
- these functions abstract the device specific implementation
of a functionality per SoC
- move them to nvhost_driver so that nvhost_device can be
instantiated from arch code using board files/device trees
- add support to use single driver for multiple devices using
concept of id_table. this will be useful in supporting
multiple SoC devices binding single driver
- also add some notes about how device name is expected
Bug 871237
Change-Id: I4c75d7121d26c3bdc50f058e0d144d89ca0edbd9
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/100985
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Remove the efficiency factor in the bandwidth calculation.
Clock API will take care off setting the right clock based factoring the
efficiency.
Change-Id: I2b549197778b5afaf1aab3cc87a84debb08172e8
Reviewed-on: http://git-master/r/91659
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/103682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Adds a global alpha parameter to each window. It provides a default
alpha value for pixel formats that do not include alpha.
Change-Id: I5465864877a727b4daed0eb32fb8219e2ccb663e
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/101806
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Bug 955184
Change-Id: I7ac0a290c2b6acd454de05d094bd676b88f4b476
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/101546
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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-Move _tegra_dc_enable to before irq_request and remove
disable_dc_irq.
-It will remove warning of "IRQ when DC not powered!".
Bug 955184
Change-Id: If9b039f3f1635d92f10bfc54af08101972fc3d57
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/101498
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Add display feature table so that user and kernel could set and
update window attributes properly.
Bug 962353
Change-Id: I08490a225892660126f3eefe4d5b7a4bb61d9bf7
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/101078
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Set default videomode during the dc probe. This patch enables
HDMI during the probe only and fixes following issues:
1. Until Xinit there was no display on HDMI.
2. Framebuffer console on HDMI needs it to be enabled well before
Xinit.
To avoide un-necessary powering on HDMI,Check HPD and enable HDMI
only if it's present.
Bug: 930136
Bug: 977705
Change-Id: Ifb71328e5df0ccbb5751669db71fd24719fe3738
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/100656
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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This reverts commit 9349cedf17f9b3c10760c8d48f831473f87a3a15.
It is reviewed on http://git-master/r/99635
It will cause HDMI power ON and emc clock bump up to 667Mhz
after resume from LP0.
bug 930136
Change-Id: I130494fdb381b3d322ac0e3fc8be2e44f2c2d7a7
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/100202
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Set default videomode during the dc probe. This patch enables
HDMI during the probe only and fixes following issues:
1. Until Xinit there was no display on HDMI.
2. Framebuffer console on HDMI needs it to be enabled well before
Xinit.
Bug: 930136
Change-Id: Ieaf5c69eefa4a6584893425ad4fd772bcd91ea11
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/99635
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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This reverts commit 90b79e5712300baab889772a5af348559ac95836.
Bug 955393
Change-Id: I0e2a15b7d0898dbbb62f09d8bd3502ec93366664
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/99261
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: Adam Cheney <acheney@nvidia.com>
Tested-by: Adam Cheney <acheney@nvidia.com>
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Change-Id: I8aa25b03fe6801882b65209cb1a6e125ef27ac2c
Signed-off-by: Michael I. Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/98319
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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add trace_printk to log useful debug information.
Bug 870685
Change-Id: I29c0b1600f234ebb06d19c8b6c713b16f6e7643c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89204
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
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TEGRA_DC_EXT_SET_LUT programmed the proper shadow registers
but did not copy the shadow registers to the active set.
Signed-off-by: Adam Cheney <acheney@nvidia.com>
bug 947281
Change-Id: Id734e128bb708f1a75c0cad22b0c51b083d8df3b
Reviewed-on: http://git-master/r/91368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Change-Id: Ib1b0fc6015a9dd45982a97231972dadba6b5a92e
Reviewed-on: http://git-master/r/96966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Handle mode set for FBIOPUT_VSCREENINFO at the end of a frame (during
vblank). This elimiates the work around that requires disabling then
enabling display to change modes.
Adds a spinlock to protect irq code from updates to tegra_dc_mode structure.
Bug 560152
Change-Id: I5d2175f01a177a32d685b46e5af4f78efeec0786
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/90688
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Change to using kbytes/sec to avoid overflowing 32-bit integer in
bandwidth calculation.
Changing efficiency adjustment to ~35%.
Bug 958016
Change-Id: Ia8bdf79e4b3e4bc65517db18d9f351a5f840805e
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/92658
Reviewed-by: Automatic_Commit_Validation_User
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Enabled recovery of DC from resetting. When underflow triggered serveral
times(current > 4 for tegra2), DC driver will reset itself to prevent
data corruption. Reopend nvhost connection when resetting finished. That
helps system to show frames instead of a blank screen again.
Fixed Bug 936613
Change-Id: I314c37258a4a446dc07167ac60d0420e79a5fb2d
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/89406
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Remove old overlay interface, it is replaced with TEGRA_DC_EXTENSIONS
External functions made static now that overlay.c no longer needs them.
Change-Id: I5d080ceb19ad90d3b5cc4bf20494c967687293a5
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/92661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Michael I Gold <gold@nvidia.com>
Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
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Set dc clock rate dynamically to requested pixel rate.
Using modes specified in monitor's EDID data.
Return mode set errors on unsupported clock tolerances.
Bug 931908
Change-Id: I60990ecbc2fbeab542987036b8ccc30b8dababe8
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/86073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Not disabling emc clock when it's being set to zero results in incorrect
reference count when a call is made to clear bandwidth. This happens when
two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle
easily shows this scenario.
With this fix, disp.emc's ref count is properly managed even after multiple
deep-sleep/wake-up cycles.
Bug 947228
Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/90100
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Bug 951626
Change-Id: Ia7c7474aa0f066cba8bd1519a98e302c4b3992e0
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/89076
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Remove unnecessary 100ms delay for primary panel since
this is needed for HDMI type only.
Bug 940012
Change-Id: Id27966fb28faa73ade3a868a9f89cadbde76e227
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/87613
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Add lock to prevent race condition between cancellation of old delayed
work and schedule of new delayed work.
Bug 936337
Change-Id: I52df82e92279163841546127c72be9879ef810d0
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/86730
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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There exits an issue that if window number is less than DC_N_WINDOWS,
window option of some windows won't be cleared. So although it should
be disabled, it might not be disabled properly. This will lead to the
failure of scan-out on screen.
Bug 943846
Change-Id: I604399abaa590b27ab4ea41ed9eb2706be16a75a
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/86230
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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GENERAL_ACT_REQ causes double-buffered registers to become active.
This register needs to be programed to reduce the latency of pixel clock after
dc enabled by tegra_dc_enable().
bug 926189
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/83346
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
(cherry picked from commit f39c5ddd1867c508900c9aa2d4eead7eb3082343)
Change-Id: I741c9be9074709c1ab571aa631cb462599d5fb78
Reviewed-on: http://git-master/r/84561
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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A V_BLANK interrupt for each frame does not allow long lp2 idle intervals.
If all windows are clean, mask V_BLANK interrupt after processing it
for updating smart dimmer. It's unmasked again when a new window update
is performed. This will schedule a work for updating smart dimmer for
the new frame.
Bug 920110
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85137
(cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6)
Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/85166
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Add a config option to limit HDMI stereo 3D output to 74.25MHz pixel clock.
When this option is set,
substitute the frame pack stereo modes
for side-by-side (half) left-right stereo modes
to meet this pixel clock restriction.
By default, do not use it (use frame packed HDMI mode as usual).
Bug 938807
Change-Id: I2ce2ca72cbb15ac1939af0f3386dd23650262435
Reviewed-on: http://git-master/r/84252
Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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When dc gets many underflows, instances of reset worker can race
to perform reset. dc ext was getting disabled outside critical region
affecting display path. disable dc ext after getting the lock.
Bug 936545
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/83108
(cherry picked from commit f9dcf7eee8ca8db28cee6fa9550044d1f746e843)
Change-Id: Ie29dc66eb52c9be472c2d0db8c0014bfe1837ad4
Reviewed-on: http://git-master/r/83406
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 932840
Change-Id: I12d8d2d2cd42d0dafea38463ad77b44f7e64d7c1
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/83645
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Enable GENERAL_ACT_REQ and HOST_TRIG_ENABLE at the same time.
Bug 930840
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/78638
(cherry picked from commit 2f78c8e3c243b4c866ad54a550167abd94c200c1)
Change-Id: If0ef97c4a2b1a0621152c02728edbbed064a5e34
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/82715
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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DC ext is enabled only from _tegra_dc_controller_enable() which is not used
from reset worker. Enable dc ext from _tegra_dc_controller_reset_enable()
as well.
Bug 933391
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/78753
(cherry picked from commit a099c612f91cc12a99325e39609b1f9001525be0)
Change-Id: Ia95df85ea602174c2fd66888b21f7a6d264c176e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/82714
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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dc irqs are required in display client disable to flag
stopping of dc stream.
Bug 930453
Reviewed-on: http://git-master/r/77808
Change-Id: I0e057ca14078d9e608cb32380123fade813c4041
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78898
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-on: http://git-master/r/76406
Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77306
Reviewed-by: Automatic_Commit_Validation_User
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Add backup clock source option in dc platform configuration. Use
backup source if fixed frequency pllp is specified as main source,
but its rate can not be divided into pixel clock within required
tolerance.
928260
Change-Id: I19bd9173276c6ea087f86361956809787875e979
Reviewed-on: http://git-master/r/76033
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76818
Reviewed-by: Automatic_Commit_Validation_User
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Use standard drvdata interface for storing and accessing nvhost_master.
Reviewed-on: http://git-master/r/72846
Change-Id: I191987c8f6d313a6ede9b59f723269cb6a197e8a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76815
Reviewed-by: Automatic_Commit_Validation_User
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When dc->emc_clk_rate goes from 0 to non-zero the dispX.emc clock is
enabled. This works with the sequence for probe and hotplug to have emc
clock in the correct enable/disable state.
Bug 927785
Bug 917769
Reviewed-on: http://git-master/r/76208
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Change-Id: I53cc8c5091967ce021dd3ec1e2bc75405dc8c45c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76813
Reviewed-by: Automatic_Commit_Validation_User
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In one-shot mode(DSI) report emc rate as disabled to reduce bandwidth in
this idle state. Use this same tegra_dc_clear_bandwidth() function to handle
display disable for all types of displays.
Bug 914917
Change-Id: I84ca1341d71999b3558f9dadb103b258a1a6ab6f
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/74652
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-on: http://git-master/r/75536
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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This reverts commit 20f43dfc590d22ad1e80b7b948f108b17038b084.
Conflicts:
drivers/video/tegra/dc/dc.c
This fix is no longer needed to boot.
Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/74884
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/75151
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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Move underflow handling out of the irq handler and into a workqueue.
Change-Id: I289d0a4c4e632a229e46d8e7f82e637409813807
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/74427
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Reviewed-on: http://git-master/r/75143
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Move all device data from nvhost_channeldesc, nvhost_moduledesc and
nvhost_module to nvhost_device. nvhost_devices are also assigned into
a hierarchy to prepare for implementation of runtime power management.
Change-Id: I1e18daae8fe538086cd1f453d316e0f73e9d7d92
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/72844
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Reviewed-on: http://git-master/r/74560
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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This reverts commit af9a6eb54c031a8cca1477134d07e1ef2b807be3.
Test reports were inconclusive on the effectiveness of this change.
Change-Id: I859a14d2e2dcd9eed3a1c64f35e4f1c077660311
Reviewed-on: http://git-master/r/74021
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Reviewed-on: http://git-master/r/74550
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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The tegra display controller supports the YUV422R planar surface format, but
this was not handled by the dc driver.
This change also fixes the YUV422RA planar format variation.
Bug 914375
Change-Id: I73ffd2f7434c71d8353c7e16ada5ac6b13fee86b
Reviewed-on: http://git-master/r/69446
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit a085ef1eeb332116f102d82af25f7a6451eb6329)
Reviewed-on: http://git-master/r/73950
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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Apply the highest bandwidth setting before windows are programmed rather
than waiting for vblank.
Bug 914917
Change-Id: Iaaede9966191fdfc896bbbb19fbbadf9c4598bff
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/72301
Reviewed-by: Michael I Gold <gold@nvidia.com>
Tested-by: Michael I Gold <gold@nvidia.com>
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Fix dc stream randomly failing to stop.
Add stablization delay during dsi interface reset.
Bug 913019
Change-Id: I1cf3013659de75d15cb1ff41b27c63abd953d614
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/71952
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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dc vsync, hsync, DE and pclk polarity in kernel
can be different with bootloader setting for a short time
when default polarity value is written.
This can generate momentary panel flicker in kernel boot.
Set the first polarity based on board dc out pin polarity
information directly if needed.
Bug 891444
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/59895
(cherry picked from commit 8e5bfd5702067309171b62a6be5471bfab68a31e)
Change-Id: I80c703792ea5a9596d4cf42ef19115cbf4d556f6
Reviewed-on: http://git-master/r/69711
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
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