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This bug was introduced by ENGR00229290 which fixed
the problem of greater than 16 LUTs used when 5-bit
waveform loaded. The bug is that now the driver is also
restricted to using 16 LUTs in 4-bit mode.
The fix is to correct the test of the EPDC_FORMAT
register used to determine if a 5-bit waveform
is loaded.
Also removed the while loop in favor of a bitwise OR
used to determine if a chosen LUT has yet to be
acknowledged by the interrupt handler.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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The wrong EPDC panel can be loaded at boot time if the machine
board file has multiple panel entries with the same video mode
parameter values. To reproduce, select a particular panel with
u-boot kernel command line parameters, for example:
video=mxcepdcfb:XYZZY
Add panel XYZZY to arch/arm/mach-mx6/board-mx6sl_evk.c after
an existing entry. Use the same video mode parameter settings
as the existing entry. On boot, the existing panel will be loaded
instead of the XYZZY panel because it comes earlier in the list
and happens to have the same video mode parameter values.
Solution: If the video mode parameter settings specified in
the call to msc_epdc_fb_set_par() match those of the panel
already loaded by mxc_epdc_fb_probe(), don't execute a
search for a new matching panel.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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When system bootup without HDMI plugin, the default modelist
and default video mode will create.
Match default video mode in default CEA modelist, make sure
default video mode is a CEA mode.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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This patch adds WXGA(1280x800@60) video mode
support to driver CHIMEI WXGA LVDS panel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 653fbb0cd709bf25942c29c0695ecc4af6987e24)
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A small logic bug prevents the init sequence from properly turning
off the clocks. This leads to the clocks being always on
if the first update does not complete due to the screen being blanked.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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Add dependency on CONFIG_FB_MXC_ELCDIF_FB, to avoid build error if as module.
Signed-off-by: Robby Cai <R63905@freescale.com>
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This is needed when build sii902x hdmi driver as module
Signed-off-by: Robby Cai <R63905@freescale.com>
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This can be detected by enabling CONFIG_LOCKDEP and CONFIG_PROVE_LOCKING
The dump log:
=============================================
[ INFO: possible recursive locking detected ]
3.0.35-02140-gb4181ce-dirty #959
---------------------------------------------
swapper/1 is trying to acquire lock:
((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88
but task is already holding lock:
((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock((fb_notifier_list).rwsem);
lock((fb_notifier_list).rwsem);
*** DEADLOCK ***
May be due to missing lock nesting notation
5 locks held by swapper/1:
#0: (&__lockdep_no_validate__){+.+.+.}, at: [<8027f244>] __driver_attach+0x48/0x98
#1: (&__lockdep_no_validate__){+.+.+.}, at: [<8027f254>] __driver_attach+0x58/0x98
#2: (registration_lock){+.+.+.}, at: [<8023a17c>] register_framebuffer+0x18/0x24c
#3: (&fb_info->lock){+.+.+.}, at: [<80238dc8>] lock_fb_info+0x18/0x3c
#4: ((fb_notifier_list).rwsem){.+.+.+}, at: [<80088758>] __blocking_notifier_call_chain+0x44/0x88
stack backtrace:
[<800405c4>] (unwind_backtrace+0x0/0xf8) from [<80097c78>] (__lock_acquire+0x1644/0x1c18)
[<80097c78>] (__lock_acquire+0x1644/0x1c18) from [<80098748>] (lock_acquire+0x84/0x98)
[<80098748>] (lock_acquire+0x84/0x98) from [<804d0aa8>] (down_read+0x34/0x44)
[<804d0aa8>] (down_read+0x34/0x44) from [<80088758>] (__blocking_notifier_call_chain+0x44/0x88)
[<80088758>] (__blocking_notifier_call_chain+0x44/0x88) from [<800887b4>] (blocking_notifier_call_chain+0x18/0x20)
[<800887b4>] (blocking_notifier_call_chain+0x18/0x20) from [<802397e0>] (fb_set_var+0x264/0x290)
[<802397e0>] (fb_set_var+0x264/0x290) from [<8024a320>] (lcd_init_fb+0x54/0x70)
[<8024a320>] (lcd_init_fb+0x54/0x70) from [<8024a3f0>] (lcd_fb_event+0x44/0xb4)
[<8024a3f0>] (lcd_fb_event+0x44/0xb4) from [<80088514>] (notifier_call_chain.isra.1+0x74/0xd0)
[<80088514>] (notifier_call_chain.isra.1+0x74/0xd0) from [<80088774>] (__blocking_notifier_call_chain+0x60/0x88)
[<80088774>] (__blocking_notifier_call_chain+0x60/0x88) from [<800887b4>] (blocking_notifier_call_chain+0x18/0x20)
[<800887b4>] (blocking_notifier_call_chain+0x18/0x20) from [<8023a2d4>] (register_framebuffer+0x170/0x24c)
[<8023a2d4>] (register_framebuffer+0x170/0x24c) from [<8024fe8c>] (mxc_elcdif_fb_probe+0x464/0x564)
[<8024fe8c>] (mxc_elcdif_fb_probe+0x464/0x564) from [<8028031c>] (platform_drv_probe+0x18/0x1c)
[<8028031c>] (platform_drv_probe+0x18/0x1c) from [<8027f0f0>] (driver_probe_device+0x90/0x19c)
[<8027f0f0>] (driver_probe_device+0x90/0x19c) from [<8027f290>] (__driver_attach+0x94/0x98)
[<8027f290>] (__driver_attach+0x94/0x98) from [<8027e2e4>] (bus_for_each_dev+0x5c/0x88)
[<8027e2e4>] (bus_for_each_dev+0x5c/0x88) from [<8027eabc>] (bus_add_driver+0x188/0x250)
[<8027eabc>] (bus_add_driver+0x188/0x250) from [<8027f750>] (driver_register+0x78/0x13c)
[<8027f750>] (driver_register+0x78/0x13c) from [<8001c838>] (mxc_elcdif_fb_init+0x38/0x48)
[<8001c838>] (mxc_elcdif_fb_init+0x38/0x48) from [<80035334>] (do_one_initcall+0x34/0x178)
[<80035334>] (do_one_initcall+0x34/0x178) from [<80008968>] (kernel_init+0x84/0x124)
[<80008968>] (kernel_init+0x84/0x124) from [<8003b614>] (kernel_thread_exit+0x0/0x8)
In fact, we don't need support dynamically switch the framebuffer.
so, we only need do once registeration in probe function.
Signed-off-by: Robby Cai <R63905@freescale.com>
Acked-by: Lily Zhang
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The EPDC set the UPD_VOID (i.e. cancelled) bit in two cases:
1. No pixels needed updating
2. All pixels collided (COL bit also set)
The driver was miss-handling case 2. This fix causes case 2
to be treated as a collision and the update to be resubmitted.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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When a 5-bit waveform is loaded, the maximum number of available
LUTs is 16. The LUT allocator must account for this.
Note that 5-bit waveform loading is currently not supported in the
driver. However, this fix makes sure the LUT allocator is correct
when 5-bit support is added.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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When suspend, the lcdif and panel will be stopped. When resume, fb_set_par()
will be called, in which the lcdif and the panel will be re-initialized.
However, fb_set_par() also checks the parameters via mxc_elcdif_fb_par_equal(),
which will probably make fb_set_par() just return with them un-initialized.
And thus, the interrupt will not come. This patch added a varible to check
whether they're running along with mxc_elcdif_fb_par_equal() checking to
fix the issue. If not running, re-initialization will be forcely done.
Signed-off-by: Robby Cai <R63905@freescale.com>
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This patch works around the 6DLS and 6SL chip errata:
ERR005313 EPDC: Incorrect data fetched when the buffer update width is
2048 pixels or greater
This patch breaks large updates into multiple updates, which works
around the problem on both 6DSL and 6SL. This patch does not use the
Group Update feature, which may improve things further on 6SL.
This patch does not include for support for any particular large panel.
It was tested on ED09705 (2400x1650). Support for ED09705 is
available in a separate patch.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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Filter out IPU framebuffer for MX6SL by adding conditional control.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Enable sii902x HDMI driver with ELCDIF framebuffer interface.
HDMI cable Hotplug support.
Video mode switch support.
Blank/Unblank HDMI display support.
Added config variable CONFIG_FB_MXC_SII902X_ELCDIF for sii902x_elcdif module
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- Added mxcfb_elcdif_register_mode function.
- Create video mode list, and check default video mode
with video mode list before setting.
- Adjust elcdif pixel clock setting, reconfig elcdif pixel
parent clock video pll, get more accurate pixel clock
according video mode.
- Added video mode dump function for debug
Signed-off-by: Sandor Yu <R01008@freescale.com>
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This patch adds late init support in IPUv3 fb driver
to avoid IPUv3 fb being re-initialized during probe if
a platform supports smooth transition from bootloader
splashimage to system UI. The re-initialization will
be delayed to the first time the user triggers
mxcfb_set_par() and unblank the framebuffer.
The following items are done to support this:
1) Move global alpha and color key setting in probe
after framebuffer is registered(before registering
we enable IPU hsp clock), because the 2 APIs enable
and disable IPU hsp clock which may cause IPU stops
running in ipuv3 fb probe function.
2) Do not clear framebuffer content in probe function
if late init is set. This is to avoid bootloader
splashimage content is cleared.
3) If late init is set, do not re-initialize and
unblank framebuffer in probe function, but initialize
and enable ipu display channel instead to enable
the ipu hsp clock. Refer to the code comment for
detail.
4) Delay register IPU interrupts used by framebuffer
until IPU hsp clock is enabled by 3). As the APIs
to register IPU interrupts may enable and disable
IPU hsp clock as well.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 926a6187d89afb5a37dc3b1f3c7bc5225742d09b)
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Users may call FBIOPUT_VSCREENINFO framebuffer ioctrl to set
a framebuffer's pixel format by specifying bits_per_pixel field
and red/green/blue/transp fields of struct fb_var_screeninfo.
Users may also know a framebuffer's pixel format at which it is
working by calling FBIOGET_VSCREENINFO framebuffer ioctrl, red/
green/blue/transp bitfields of struct fb_var_screeninfo tell the
exact offset and length of each color component in a pixel. This
patch supports RGB24/RGB32/ABGR32 pixel formats with these 2 ioctrls.
To change the default pixel format when initializeing a framebuffer
at the first time, users may add 'fbpix=' option in framebuffer
kernel command line option, for example, 'video=mxcfb0:fbpix=ABGR32'
makes fb0's default pixel format be ABGR32. 'bpp=' option cannot
overwrite 'fbpix=' option, for example, 'video=mxfb0:fbpix=RGB24,
bpp=16' still makes fb0 work at RGB24 by default. To be back
compatible, this patch doesn't change the default pixel formats
(BGR24/BGR32/RGB565) for each bits_per_pixel, if users don't
provide valid 'fbpix=' option.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch corrects the logic to check BGR24 pixel format for
'if=' option in kernel bootup command line of framebuffer.
After applying the patch, users may use 'if=BGR24' to specify
the display data format to be BGR24. For example, 'video=mxcfb0:
dev=lcd,LCD_VIDEO_NAME,if=BGR24' makes IPUv3 output BGR24 data
to fb0's lcd panel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 7ab85674f63eb1388e44a61e17891f0e283c409a)
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Adding Atkinson's dithering alorism implementation into our EPDC
Driver with Y8->Y1 and Y8->Y4 supported. Two EPDC flags have been
added to support the features. EPDC_FLAG_USE_DITHERING_Y1 and
EPDC_FLAG_USE_DITHERING_Y4.
Signed-off-by: Daiyu Ko <dko@freescale.com>
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Fix HDMI build warning.
drivers/video/mxc_hdmi.c: In function 'mxc_hdmi_set_mode':
drivers/video/mxc_hdmi.c:1659: warning: assignment discards
qualifiers from pointer target type
drivers/video/mxc_hdmi.c: At top level:
driver/video/mxc_hdmi.c:1398: warning: 'mxc_hdmi_enable_pins'
defined but not used
Remove unused function mxc_hdmi_enable_pins() and mxc_hdmi_disable_pins()
from code. Fix defined but unused function build warning.
Added pointer conversion from const poniter to non-const pointer.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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HDMI PHY init function will been called four times during system resume.
The first call before pixel clock enable, so it will print
PHY PLL unlock message, but the PHY PLL will locked in the next
three times called. It will not affect HDMI PHY function.
Change message print function dev_err to dev_dbg.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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In this patch:
1. Close audio PCM stream when video unblank and plugout event happens.
2. Set HDMI cable and blank state into HDMI core driver when
plug/unplug, blank/unblank events happens.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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Bootup Android without HDMI cable plugin, then plugin HDMI cable,
video mode in /sys/class/graphics/fb0/mode not same as actually
HDMI work video mode.
The root cause is in video mode point to one of video mode in
original video modelist, but the modelist will be updated when
HDMI cable plug to new monitor.
If HDMI original worked video mode can work on new monitor,
the HDMI and framebuffer will not updated, so HDMI actually
work mode not same as /sys/class/graphics/fb0/mode
Updated fbi mode pointer even if video mode no changed
in case moselist is updated, the issue will fixed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 67c2bd5edef363412a074e9b4130b5207dac8a7f)
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Disable LDB DI clock when suspend.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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EDID read will failed sometimes on some boards.
Read EDID twice if first one failed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Some TV support specific video mode that different with
CEA standard, and it's pixel clock not comply CEA standard.
But audio configuration paramter N and CTS should follow CEA standard.
So audio may not work in these specific video mode.
Filter video mode get from EDID, only keep standard CEA video mode
in the modelist.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Allocate DMA buffer from DMA zone, and the system can configure reserve dma
size through proc fs file under /proc/sys/vm/lowmem_reserve_ratio.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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If using mxcfb1 for HDMI display, it will print
'PHY PLL not locked'.
Fixed it with setting HDMI default to blank state.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Need to enable both axi and pix clock before doing EPDC reset,
or the hardware reset will fail, which will result in dead loop
of EPDC resume function, and block system resume.
Signed-off-by: Anson Huang <b20788@freescale.com>
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HDMI enable/disable_pins setting HDMI DDC enable, but the pins confilct
with I2C2 bus on board design, so only HDCP function is enable
the function can been called.
Remove enable/disable_pins in blank/unblank function to make sure
I2C2 bus can work when HDCP disable.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support
Signed-off-by: Wayne Zou <b36644@freescale.com>
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- Add early param to select SPDC module, which can enable SPDC and
EPDC modules build in kernel. Fix the build error because they both
modules use the same gobal varaible.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Added HDMI vendor specific data block parse to MXC EDID code.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Check HDMI VSDB block, only enable HDMI output when EDID with HDMI
VSDB block, enable DVI output when EDID with no HDMI VSDB.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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HDMI not support deep color output, setting register
VP_PR_CD bits color_depth to 0.(24 bits per pixel video)
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Really disable pix/axi clock when SPDC is idle.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Because we have DISPLAY power down/up request when do suspend/resume,
EPDC/SPDC has been powered off and powered on again, thus re-initialization
is needed.
Signed-off-by: Robby Cai <R63905@freescale.com>
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If LUT 63 is busy and LUTs 0-31 are busy, the epdc_choose_next_lut
function was not correctly selecting an available LUT between 32-62.
Instead, it was returning 0. This fixes that issue by properly
offsetting the available LUT from the second 32-bit segment of the
64-bit LUT field.
Signed-off-by: Danny Nold <dannynold@freescale.com>
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Export function mxc_edid_parse_ext_blk.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- Add MXC HDMI CEC to kconfig and makefile under driver/mxc
- Add initial mxc_hdmi-cec.c file to provide basic HDMI CEC
functionality:
- Basic HDMI CEC resource initilize functional
- Support for sending and receiving CEC message via CEC line
- Report HDMI cable status to CEC lib at userspace.
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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HDMI Hotplug function should work when display blank,
So keep HDMI HPD clock on.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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In the HDMI PHY internal, there are two register that can adjust
waveform of eyediagram.
0x0e -- voltage level control; it can adjust the single end data signals;
0x09 -- define pre-emphasis factor;
(it will affect the rise time and fall time of D0/D1/D2);
Adjust HDMI PHY register 0x09 and 0xe for MX6DL SabreSD and MX6Q SabreSD
waveform of eyediagram to pass HDMI compliance test electrical test case.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- Kernel will print dma free warning when no Sipix panel
connect. Fix dma free unmatched size.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Not update FB var if video mode same as last HDMI cable plugout.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Clean up the fb driver for maintainability:
1. Use completion instead of semaphore API interface.
2. Use IPU oneshot interrupt mode and remove ipu_disable_irq()
function call in interrupt handler.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Save overlay offset before DP disable and restore it after DP enable.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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The issue only in play video on DP FG, no such issue on DP BG.
HDMI drvier will call fb_set_var to config framebuffer after HDMI cable plugin.
In Frame buffer driver, the DP FG and BG register as different fb.
The function fb_set_var only update one fb.
As IPU DP module, if DP BG is re-enabled, the FG should reconfig again.
So after HDMI plugin, only BG fb is update, FG fb will work incorrect,
no end of frame interrupt trigger, and print
"mxc_sdc_fb mxc_sdc_fb.0: timeout when waiting for flip irq"
to display.
Change code in function fb_set_var, FG fb will reconfig with DP BG fb.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Added hdmi clock gating/ungating when devide suspend/resume
Signed-off-by: Sandor Yu <R01008@freescale.com>
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