| Age | Commit message (Collapse) | Author |
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Hwcomposer check this return value and will crash due to init failure rarely.
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Lily Zhang
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Enable the EDO mode for mx6q.
The following is the test result with the same nand chip (Micron MT29F32G08QAA)
in mode 4:
The test result without enable the EDO mode:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
mtd_speedtest: scanned 400 eraseblocks, 6 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 1945 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3384 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 1841 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3136 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 1853 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3164 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 145441 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 146711 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 147139 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 147786 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 147569 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 147677 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 147677 KiB/s
mtd_speedtest: finished
=================================================
The test result enable the EDO mode:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
mtd_speedtest: scanned 400 eraseblocks, 6 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 3733 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 20413 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 3603 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 18966 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 3668 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 19686 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 146604 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 147354 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 147677 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 148002 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 147894 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 148329 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 148220 KiB/s
mtd_speedtest: finished
=================================================
We can see that there is 6 times performance improvement for reading
when we enable the EDO mode.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
This field is used as delay for gpmi write strobe.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The current code will gets the clock frequency which is used by
gpmi_nfc_compute_hardware_timing(). It makes the code a little mess.
So move the `get clock frequency` code to the
gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy
and clean.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.
This patch also changs some comments to make the code more readable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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i2c device (isl29023) can not suspend once during hdmi
audio suspend/resume test, and print log:
pm_op(): i2c_device_pm_suspend+0x0/0x38 returns -4 PM: Device
2-0044 failed to suspend: error -4 PM: Some devices failed to
suspend PM: resume of devices complete after 40.936 msecs
Restarting tasks ... done.
Because suspend function in isl29023 driver requires i2c bus
to write isl29023 device. I2C apdater driver process any signal
as exception during waiting the bus idle, so once user space sent
out signal during suspend, I2C device cannot request bus.
Using "fatal_signal_pending()" instead of "signal_pending()"
to avoid the waiting of bus idle to be terminated by general
signals except SIGKILL. After the change, i2c adapter can be
terminated by kill signal from user space with "CTRL+C" or
kill command operation.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Ethernet performance is downgraded when wait mode on in
100Mbps mode.
wait mode off:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
wait mode on:
100Mbps mode: tx bandwidth is 30Mbps
rx bandwidth is 94Mbps
After apply the patch:
wait mode on:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
Wait mode on cause enet interrupt has long latency, which
results in BD entries are full and stop tx queue, so cpus
have more chance to enter wait mode.
Incresing TX BD entries can properly accommodate the blance
between BD request before tx packets and BD release after tx
completion in interrupt process.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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If in the early suspend mode without any other
wakelock except the gadget one, user unplug the
usb cable, the gadget udc suspend callback will
be called, and it releases the wakelock immediately.
At this time, the wake_unlock function will wakeup
the suspend workqueue to do system suspend, and
udc driver's status change can not be finished
before suspend. This causes replug in the usb cable
after resume, WinXP can not start the MTP correctly.
Just re-lock that wakelock for about 500ms in the
udc suspend callback does fix this issue.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Ethernet performance is downgraded when wait mode on in
100Mbps mode.
wait mode off:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
wait mode on:
100Mbps mode: tx bandwidth is 30Mbps
rx bandwidth is 94Mbps
After apply the patch:
wait mode on:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
Wait mode on cause enet interrupt has long latency, which
results in BD entries are full and stop tx queue, so cpus
have more chance to enter wait mode.
Incresing TX BD entries can properly accommodate the blance
between BD request before tx packets and BD release after tx
complete in interrupt process.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Conflicts:
arch/arm/mach-mx6/pm.c
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We should make sure clk_enable is called after clk_get.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Previous temperature range is -25C ~ 125C, according to latest
datasheet, change it to -40C to 125C.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix HDMI build warning.
drivers/video/mxc_hdmi.c: In function 'mxc_hdmi_set_mode':
drivers/video/mxc_hdmi.c:1659: warning: assignment discards
qualifiers from pointer target type
drivers/video/mxc_hdmi.c: At top level:
driver/video/mxc_hdmi.c:1398: warning: 'mxc_hdmi_enable_pins'
defined but not used
Remove unused function mxc_hdmi_enable_pins() and mxc_hdmi_disable_pins()
from code. Fix defined but unused function build warning.
Added pointer conversion from const poniter to non-const pointer.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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1.config gpio dok for AC charger as wake up irq, config gpio uok
for USB charger as wake up irq.
2.add AC/USB charger detect in resume,fix charger detect status update
missing after attach AC/USB charger and resume system
Signed-off-by: Rong Dian <b38775@freescale.com>
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HDMI PHY init function will been called four times during system resume.
The first call before pixel clock enable, so it will print
PHY PLL unlock message, but the PHY PLL will locked in the next
three times called. It will not affect HDMI PHY function.
Change message print function dev_err to dev_dbg.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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1) In the interrupt handler, we access sync interrupt
control registers 2 times, and each time with spin
lock being held and then released, which may cause
potential racing on the registers. We see that
as long as the racing happens with two displays
enabled on the same IPU, one IPU display channel
will lose EOF interrupt and it makes its fb's pan
display ioctrl fail with timeout. This patch changes
to hold the spin lock one time for the whole irq
handler, as the handler should return quickly.
Holding and releasing the spin lock unnecessarily
may bring performance penalty as well.
2) We do not need to use spin_lock_irqsave() and
spin_unlock_irqrestore() in the interrupt handler,
as we are already in the hard irq context. Using
spin_lock() and spin_unlock() is enough to protect
the registers.
3) Clear an interrupt control bit as soon as its related
handler finishes.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c5d3731fa0880a65efafb4826d3722aacb79edd5)
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As we define ERR interrupt with 0 irq resource id and SYNC
interrupt with 1 irq resource id in platform-imx_ipuv3.c,
we wrongly assign them in IPUv3 driver.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 52c9fc323e0f72e53de6fe0c6f7012fe7adf14b4)
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HMAC keys often need to be reduced to under the size of a digest to
be used. The driver does this psuedo-synchronously through the use of
hash_digest_key(), which builds a sequence pointered job descriptor to
perform this function.
When this function built the job descriptor, it correctly accounted for the
number of instructions and number of pointers that would go into its
construction. However, it failed to account for the fact that both the
sequence in and out pointers used extended lengths, adding 8 more bytes to
the required job descriptor. This caused the descriptor to overrun the
allocated buffer by that amount, resulting in memory corruptions.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Multiple function in asynchronous hashing use a saved-state block,
a.k.a. struct caam_hash_state, which holds a stash of information
between requests (init/update/final). Certain values in this state
block are loaded for processing using an inline-if, and when this
is done, the potential for uninitialized data can pose conflicts.
Therefore, this patch improves initialization of state data to
prevent false assignments using uninitialized data in the state block.
This patch addresses the following traceback, originating in
ahash_final_ctx(), although a problem like this could certainly
exhibit other symptoms:
kernel BUG at arch/arm/mm/dma-mapping.c:465!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
Internal error: Oops: 805 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 Not tainted (3.0.15-01752-gdd441b9-dirty #40)
PC is at __bug+0x1c/0x28
LR is at __bug+0x18/0x28
pc : [<80043240>] lr : [<8004323c>] psr: 60000013
sp : e423fd98 ip : 60000013 fp : 0000001c
r10: e4191b84 r9 : 00000020 r8 : 00000009
r7 : 88005038 r6 : 00000001 r5 : 2d676572 r4 : e4191a60
r3 : 00000000 r2 : 00000001 r1 : 60000093 r0 : 00000033
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 1000404a DAC: 00000015
Process cryptomgr_test (pid: 1306, stack limit = 0xe423e2f0)
Stack: (0xe423fd98 to 0xe4240000)
fd80: 11807fd1 80048544
fda0: 88005000 e4191a00 e5178040 8039dda0 00000000 00000014 2d676572 e4191008
fdc0: 88005018 e4191a60 00100100 e4191a00 00000000 8039ce0c e423fea8 00000007
fde0: e4191a00 e4227000 e5178000 8039ce18 e419183c 80203808 80a94a44 00000006
fe00: 00000000 80207180 00000000 00000006 e423ff08 00000000 00000007 e5178000
fe20: e41918a4 80a949b4 8c4844e2 00000000 00000049 74227000 8c4844e2 00000e90
fe40: 0000000e 74227e90 ffff8c58 80ac29e0 e423fed4 8006a350 8c81625c e423ff5c
fe60: 00008576 e4002500 00000003 00030010 e4002500 00000003 e5180000 e4002500
fe80: e5178000 800e6d24 007fffff 00000000 00000010 e4001280 e4002500 60000013
fea0: 000000d0 804df078 00000000 00000000 00000000 00000000 00000000 00000000
fec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
fee0: 00000000 00000000 e4227000 e4226000 e4753000 e4752000 e40a5000 e40a4000
ff00: e41e7000 e41e6000 00000000 00000000 00000000 e423ff14 e423ff14 00000000
ff20: 00000400 804f9080 e5178000 e4db0b40 00000000 e4db0b80 0000047c 00000400
ff40: 00000000 8020758c 00000400 ffffffff 0000008a 00000000 e4db0b40 80206e00
ff60: e4049dbc 00000000 00000000 00000003 e423ffa4 80062978 e41a8bfc 00000000
ff80: 00000000 e4049db4 00000013 e4049db0 00000013 00000000 00000000 00000000
ffa0: e4db0b40 e4db0b40 80204cbc 00000013 00000000 00000000 00000000 80204cfc
ffc0: e4049da0 80089544 80040a40 00000000 e4db0b40 00000000 00000000 00000000
ffe0: e423ffe0 e423ffe0 e4049da0 800894c4 80040a40 80040a40 00000000 00000000
[<80043240>] (__bug+0x1c/0x28) from [<80048544>] (___dma_single_dev_to_cpu+0x84)
[<80048544>] (___dma_single_dev_to_cpu+0x84/0x94) from [<8039dda0>] (ahash_fina)
[<8039dda0>] (ahash_final_ctx+0x180/0x428) from [<8039ce18>] (ahash_final+0xc/0)
[<8039ce18>] (ahash_final+0xc/0x10) from [<80203808>] (crypto_ahash_op+0x28/0xc)
[<80203808>] (crypto_ahash_op+0x28/0xc0) from [<80207180>] (test_hash+0x214/0x5)
[<80207180>] (test_hash+0x214/0x5b8) from [<8020758c>] (alg_test_hash+0x68/0x8c)
[<8020758c>] (alg_test_hash+0x68/0x8c) from [<80206e00>] (alg_test+0x7c/0x1b8)
[<80206e00>] (alg_test+0x7c/0x1b8) from [<80204cfc>] (cryptomgr_test+0x40/0x48)
[<80204cfc>] (cryptomgr_test+0x40/0x48) from [<80089544>] (kthread+0x80/0x88)
[<80089544>] (kthread+0x80/0x88) from [<80040a40>] (kernel_thread_exit+0x0/0x8)
Code: e59f0010 e1a01003 eb126a8d e3a03000 (e5833000)
---[ end trace d52a403a1d1eaa86 ]---
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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A workaround to eMMC/SD interrupt timeout issue.
The host->clk_status has race condition issue.
It has chance that we disable the clock when
there's cmd/data requesting.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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1) In the interrupt handler, we access sync interrupt
control registers 2 times, and each time with spin
lock being held and then released, which may cause
potential racing on the registers. We see that
as long as the racing happens with two displays
enabled on the same IPU, one IPU display channel
will lose EOF interrupt and it makes its fb's pan
display ioctrl fail with timeout. This patch changes
to hold the spin lock one time for the whole irq
handler, as the handler should return quickly.
Holding and releasing the spin lock unnecessarily
may bring performance penalty as well.
2) We do not need to use spin_lock_irqsave() and
spin_unlock_irqrestore() in the interrupt handler,
as we are already in the hard irq context. Using
spin_lock() and spin_unlock() is enough to protect
the registers.
3) Clear an interrupt control bit as soon as its related
handler finishes.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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As we define ERR interrupt with 0 irq resource id and SYNC
interrupt with 1 irq resource id in platform-imx_ipuv3.c,
we wrongly assign them in IPUv3 driver.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Conflicts:
arch/arm/mach-mx6/board-mx6q_sabresd.c
arch/arm/mach-mx6/board-mx6sl_arm2.c
arch/arm/mach-mx6/bus_freq.c
arch/arm/mach-mx6/cpu_op-mx6.c
arch/arm/plat-mxc/cpufreq.c
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In this patch:
1. Close audio PCM stream when video unblank and plugout event happens.
2. Set HDMI cable and blank state into HDMI core driver when
plug/unplug, blank/unblank events happens.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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In this patch, add support for:
1. Interface for HDMI audio to register PCM into HDMI core driver.
2. Interface for HDMI video driver to stop HDMI audio
3. Interface for HDMI video driver to inform the state of HDMI cable and
state of HDMI blank.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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add sys_close() to close opened file in cooling device
Signed-off-by: Rong Dian <b38775@freescale.com>
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Bootup Android without HDMI cable plugin, then plugin HDMI cable,
video mode in /sys/class/graphics/fb0/mode not same as actually
HDMI work video mode.
The root cause is in video mode point to one of video mode in
original video modelist, but the modelist will be updated when
HDMI cable plug to new monitor.
If HDMI original worked video mode can work on new monitor,
the HDMI and framebuffer will not updated, so HDMI actually
work mode not same as /sys/class/graphics/fb0/mode
Updated fbi mode pointer even if video mode no changed
in case moselist is updated, the issue will fixed.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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return error number when set camera change mode fail, if not the
driver may continue to setup the video processing with wrong parameter.
Signed-off-by: Yuxi Sun <b36102@freescale.com>
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Add V4L2 support -- driver part.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Set correct PITCH (aka, stride) for AS, PS, Output buffer.
This is needed for V4L2.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Replace BUG macro with error message
Signed-off-by: Wayne Zou <b36644@freescale.com>
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Avoid release resource twice when timeout happen.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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At pc sends suspend/resume case, the udc_controller->usb_state should
keep unchange during the suspend/resume process, at former code, the
fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED
unconditionally. In fact, USB_STATE_ATTACHED stands for initial state
and should be set when we try to run controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Since Logitech Quickcam E3500 is defaultly listed in usb_quirk_list on current
linux kernel. So the USB camera only supports reset resume, but doesn't support
normal usb suspend/resume. Actually, the USB camera works abnormally after USB
reset resume, but it works well after doing normal suspend/resume.
Signed-off-by: make shi <b15407@freescale.com>
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Vsync-pre irq is invalid for IPU overlay channel. The fb driver code
wrongly registers Vsync-pre for overlay channel with an un-initialized
irq number(0), which is conflict with CSI EOF irq number and causes
capture function broken. This patch avoids registering vsync-pre irq
for overlay channel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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- invalid data preparation is a reasonable path, so no need to set to
WARNING level, change it to DEBUG level.
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Move spin_unlock_irqrestore to avoid calling mutex at atomic
environment, as dr_wake_up_enable will call mutex_lock
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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IPU: Clean up dead code
Signed-off-by: Wayne Zou <b36644@freescale.com>
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If we use the late_initcall(), then there is a time slot between
the exit of early uart console and the real console:
-->late_initcall(mxc_early_uart_console_disable)
......
-->imx_startup()
In this time slot, the clock will be closed, so the log printed during
the time slot is buffered, this is why we can not see the NFS's log.
Change the late_initcall() to late_initcall_sync() which eliminates the
time slot.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
Signed-off-by: Rong Dian <b38775@freescale.com>
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Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
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Test Env:
1. MX6DL SabreSD board.
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52MHz.
3. Test commands:
3.1 Writing command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Performance result with this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~11MB/s (w) | ~5MB/s (w) | ~11MB/s (w) |
| | ~25MB/s (r) | ~25MB/s (r) | ~23MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~5MB/s (w) | ~9MB/s (w) |
| | ~16MB/s (r) | ~20MB/s (r) | ~13MB/s (r) |
-------------------------------------------------------
Performance result without this patch:
-------------------------------------------------------
| CPU freq | SDMA (512KB) | SDMA (64KB) | ADMA |
|----------+--------------+-------------+-------------|
| 1Ghz | ~10MB/s (w) | ~5MB/s (w) | ~10MB/s (w) |
| | ~22MB/s (r) | ~23MB/s (r) | ~22MB/s (r) |
|----------+--------------+-------------+-------------|
| 200Mhz | ~8MB/s (w) | ~4MB/s (w) | ~8MB/s (w) |
| | ~13MB/s (r) | ~16MB/s (r) | ~11MB/s (r) |
-------------------------------------------------------
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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