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2016-06-29video: tegra: correct lvds clk sequenceMarcel Ziswiler
Patch taken from Manoj Gupta's post on NVIDIA's public embedded systems forum: https://devtalk.nvidia.com/default/topic/822612/jetson-tk1/-issue-lvds-panel-enabled-effect-hdmi-out-image-pull-down-menu-items/post/4673174/#4673174 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2016-06-29video: tegra: fix build with enabled tegra lvds driverMarcel Ziswiler
This fixes the following build time error in case CONFIG_TEGRA_LVDS is enabled: drivers/video/tegra/dc/sor.h: In function 'tegra_sor_clk_enable': drivers/video/tegra/dc/sor.h:180:2: error: implicit declaration of function 'clk_prepare_enable' [-Werror=implicit-function-declaration] clk_prepare_enable(sor->sor_clk); ^ drivers/video/tegra/dc/sor.h: In function 'tegra_sor_clk_disable': drivers/video/tegra/dc/sor.h:185:2: error: implicit declaration of function 'clk_disable_unprepare' [-Werror=implicit-function-declaration] clk_disable_unprepare(sor->sor_clk); ^ In file included from drivers/video/tegra/dc/dc_priv_defs.h:26:0, from drivers/video/tegra/dc/dc_priv.h:23, from drivers/video/tegra/dc/lvds.c:23: include/linux/clk.h: At top level: include/linux/clk.h:330:19: error: static declaration of 'clk_prepare_enable' follows non-static declaration static inline int clk_prepare_enable(struct clk *clk) ^ In file included from drivers/video/tegra/dc/lvds.h:20:0, from drivers/video/tegra/dc/lvds.c:22: drivers/video/tegra/dc/sor.h:180:2: note: previous implicit declaration of 'clk_prepare_enable' was here clk_prepare_enable(sor->sor_clk); ^ In file included from drivers/video/tegra/dc/dc_priv_defs.h:26:0, from drivers/video/tegra/dc/dc_priv.h:23, from drivers/video/tegra/dc/lvds.c:23: include/linux/clk.h:345:20: error: conflicting types for 'clk_disable_unprepare' [-Werror] static inline void clk_disable_unprepare(struct clk *clk) ^ include/linux/clk.h:345:20: error: static declaration of 'clk_disable_unprepare' follows non-static declaration In file included from drivers/video/tegra/dc/lvds.h:20:0, from drivers/video/tegra/dc/lvds.c:22: drivers/video/tegra/dc/sor.h:185:2: note: previous implicit declaration of 'clk_disable_unprepare' was here clk_disable_unprepare(sor->sor_clk); ^ Final patch taken from Manoj Gupta's post on NVIDIA's public embedded systems forum: https://devtalk.nvidia.com/default/topic/822612/jetson-tk1/-issue-lvds-panel-enabled-effect-hdmi-out-image-pull-down-menu-items/post/4663817/#4663817 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2016-06-29mmc: tegra: apalis-tk1: hack to make sd1 functionalMarcel Ziswiler
Disable the external loopback and use the internal loopback as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM. Enable card detect polling as we can't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it features some magic properties even though the external loopback is disabled and the internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2016-06-29apalis_t30/tk1: igb: no nvm and Ethernet MAC address handlingMarcel Ziswiler
Springville/i211 with a blank Flash/iNVM use different PCI IDs. Extend the driver to load despite i210/i211 data sheets claiming tools only, not for driver. Only warn rather than fail on NVM validation failures on Apalis T30. Revise Ethernet MAC address assignment: should now handle up to two instances of custom user MACs (2nd one with a 0x100000 offset). This way customer does not have to worry about NVM on a secondary Ethernet on the carrier board and still gets a valid official MAC address from us (e.g. analogous to how we did it on our Protea carrier board). Use the Toradex OUI as default MAC address if no valid one is encountered. Tested on samples of Apalis T30 2GB V1.0B, V1.0C, V1.1A, Apalis T30 1GB V1.0A, V1.1A and Apalis T30 1GB IT V1.1A both with blank NVMs as well as iNVMs programmed with Intel's defaults. Tested on samples of Apalis TK1 2GB V1.0A and V1.0B both with blank NVMs as well as iNVMs programmed with Intel's defaults. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> (cherry picked from commit c4c3c7449bdb15c53bfebb0a29c73b24ea810d23)
2016-06-29igb: integrate tools only device supportMarcel Ziswiler
Springville/i211 with a blank Flash/iNVM use a different PCI ID (tools only, not for driver) than properly programmed ones. While at it also fix ethtool time stamping as well as RX flow hash indirection functionality. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> (cherry picked from commit 2c7123458270c9b3ec9b5ed668f9d55a7f8dbad9)
2016-06-29igb: integrate igb driver 5.3.5.3Marcel Ziswiler
Integrate latest igb driver version 5.3.5.3 (igb-5.3.5.3.tar.gz from e1000.sf.net). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2016-06-29Revert "mmc: enable flag for disabling access to boot partitions"Marcel Ziswiler
This reverts commit ca90caa335e3ded32ad6b0a92ad0fa00b67b2322. We do require eMMC hardware area boot partition access for fw-util aka U-Boot envrionment access. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2016-06-16mmc: Allow forward compatibility for eMMCRomain Izard
As stated by the eMMC 5.0 specification, a chip should not be rejected only because of the revision stated in the EXT_CSD_REV field of the EXT_CSD register. Remove the control on this value, the control of the CSD_STRUCTURE field should be sufficient to reject future incompatible changes. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> (cherry picked from commit 03a59437ef6b6ad7fb0165cb9b96c08d6bf057fc)
2016-05-27ata: ahci_tegra: disable DIPMtegra-l4t-r21.5Preetham Chandru R
DIPM is not a POR for Tegra AHCI Sata Controller Bug 200087528 Change-Id: I5a742170177c9f57426f3756a8cfafefa88af92b Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: http://git-master/r/1013776 (cherry picked from commit 7ebd3b1058491ee87686e9e731b79ecd914e00d9) Reviewed-on: http://git-master/r/1031624 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2016-05-26platform: tegra: nvavp: fix for pre-decrement of clk_enabled cntrBhushan Rupde
Bug 1729847 Change-Id: Ie455b0469a1d4e35453ca9e36c5e90dfdc6f56a2 Signed-off-by: Bhushan Rupde <brupde@nvidia.com> Reviewed-on: http://git-master/r/1147432 Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com> Reviewed-by: Soumen Dey <sdey@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-05-24video: tegra: host: Fix ch open error handlingArto Merilainen
In case kernel fails to open a channel (e.g. due to inability to allocate hardware context or turn on the device), the channel open function releases the resources that were already allocated successfully. However, currently the error path additionally calls the channel release function for putting the channel pointer after the private data structures have been freed - thereby causing use-after-free memory usage. This patch reworks error handling in channel open to release channel without risking usage of already freed memory. Bug 1763577 Change-Id: Ic7562e69f2babad653afc7a11e413701494a30b4 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/1148081 Reviewed-by: Winnie Hsu <whsu@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com>
2016-05-23video: tegra: host: check if offset is u32 alignedDeepak Nibade
In nvhost_ioctl_ctrl_module_regrdwr(), we copy offset to read/write from user space but we do not have any check on it So it is possible for user space to add unaligned offset and request read/write which would crash the system Fix this by explicitly checking alignment of the offset passed by user space Bug 1739935 Change-Id: Iea2a07c60500af876b732a0e9d9d08535aa53b5c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1029405 (cherry picked from commit 422baa09a17a6a17f4e572aa5441ca174634de0d) Reviewed-on: http://git-master/r/1123363 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2016-05-23camera: tegra: Fix security vulnerability issueFrank Chen
Deprecate outdated UPDATE_GPIO function in camera.pcl driver. This function is not used by any code anymore and is a security vulnerability since it is trying to access user mode pointer directly. Bug 1745102 Change-Id: I4e7e5f9c186f980dcadfe52ec4284102255f19cf Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: http://git-master/r/1115302 (cherry picked from commit 2e5c355c904a19d71456a04c70f3fb4fc7d918b0) Reviewed-on: http://git-master/r/1123362 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2016-05-20camera: tegra: Fix security vulnerability issueFrank Chen
We need to validate power on/off function size passed in from user mode in order to avoid integer overflow or out of memory failures. Bug 1745100 Change-Id: Idddd848f7dc1e864559ad219f9204325128484e5 Signed-off-by: Frank Chen <frankc@nvidia.com> Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1114354 (cherry picked from commit 8b3afcc132882f3102083f9a24de7f55476ca59b) Reviewed-on: http://git-master/r/1150944 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2016-05-20media: tegra: camera: Fix stack overreadAmey Asgaonkar
We are not checking a variable which is user controlled. This can lead to reading of the stack data. Adding a check to ensure it is less than the max possible value of the variable. Bug 1763649 Change-Id: I395e882d030199bdd7684837906a9b5d60741650 Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com> Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1150943 GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2016-04-28video: tegra: nvmap: Add ref count in nvmap_vma_listSri Krishna chowdary
Add ref count to prevent invalid vma removal from the h->vmas list and also allow addition of a different vma which also has same nvmap_vma_priv as vm_private_data into the h->vmas list. Both cases are allowed in valid usage of nvmap_vma_open/nvmap_vma_close. Bug 200164002 Change-Id: Ifc4d281dd91e1d072a9a3ee85e925040bd65a6bc Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/1133708 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2016-04-28[media] v4l: vb2-dma-contig: fix vb2_get_vma()Sri Krishna chowdary
nvmap expects that same VMA is opened and closed to disallow memory leaks. So, nvmap panics if a previously non-existent vma is being closed through it. Hence modify the sequence in vb2_get_vma() to open the vma_copy before returning it. This way nvmap sees that the vma_copy exists in its list and will close the vma. Bug 200164002 Change-Id: I45dfb8ca710375a0e70d9802ebdcc9fd4d0b4600 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/931997 (cherry picked from commit bf1d15d8a879a599f9801310cecbbb61ea60e931) Reviewed-on: http://git-master/r/1133707 Tested-by: Bryan Wu <pengw@nvidia.com> Reviewed-by: Bryan Wu <pengw@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2016-04-05media: tegra: nvavp: Fix reloc offset checkSomu Sundaram
- Check whether command buffer data offset is 32-bit aligned - Check whether relocation offset is 32-bit aligned and calculated offset is within command buffer size - Check whether target offset is 32-bit aligned and derived address is within target buffer size Bug 1741516 Change-Id: Ie5370bc1538c8cf9a702904fb88eb850baeb063d Signed-off-by: Somu Sundaram <somasundaram@nvidia.com> Reviewed-on: http://git-master/r/1113949 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Somu Sundaram <somasundarams@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-04-05media: tegra: nvavp: Fix arbitrary kernel writeSomu Sundaram
Add checks for command buffer offset, relocation offset in command buffer and target offset for patching relocation to prevent aritrary kernel write Bug 1741516 Change-Id: Ia6183ca75f983c0ede23606be9e5d824aa5fa41d Signed-off-by: Somu Sundaram <somasundaram@nvidia.com> Reviewed-on: http://git-master/r/1111699 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro <mapedro@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Somu Sundaram <somasundarams@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-03-16media: tegra: nvavp: Fix heap overflowSomasundaram S
Increase NVAVP_MAX_RELOCATION_COUNT to max. possible value and add check to return error if num_relocs in nvavp_pushbuffer_submit_ioctl exceeds NVAVP_MAX_RELOCATION_COUNT Bug 1739930 Change-Id: Ief36cedd692aa53135fc6a0039b19f18609259dd Signed-off-by: Somasundaram S <somasundaram@nvidia.com> Reviewed-on: http://git-master/r/1030885 Tested-by: Somu Sundaram <somasundarams@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-03-14gpu: nvgpu: validate wait notification offsetKonsta Holtta
Make sure that the notification object fits within the supplied buffer. Bug 1739182 Change-Id: Ifb66f848e3758438f37645be6f534f5b60260214 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1026431 (cherry picked from commit 2484c47f123c717030aa00253446e8756e1a0807) Reviewed-on: http://git-master/r/1030663 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com>
2016-03-14gpu: nvgpu: validate error notifier offsetKonsta Holtta
Make sure that the notifier object fits within the supplied buffer. Bug 1739183 Bug 1739932 Change-Id: I713574ce797ffc23cec10b5114f469dbadc68f1e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1026410 (cherry picked from commit f476b93eb19b962b8760457102448bd533efc54d) Reviewed-on: http://git-master/r/1029379 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-03-14video: tegra: host: validate error notifier offsetKonsta Holtta
Make sure that the notifier object fits within the supplied buffer. Bug 1739183 Change-Id: Ifbf46eddea86bedf0236851ea1c3f73e5f820beb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1026409 (cherry picked from commit 4086d2137e9b51137aa335fa264d924c73dea5fc) Reviewed-on: http://git-master/r/1029074 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2016-01-12watchdog: remove timeout setting in open callJeetesh Burman
timeout should not be set as part of open call. It should be set as part of Probe if watchdog enabled on probe, Otherwise timeout should be 0 since watchdog is not enabled. Bug 200160105 Change-Id: I2bc0f35436dafd01d17e3ea2ec5459fd0d75af5a Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Reviewed-on: http://git-master/r/927429 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-12-10tegra: ictlr: clear error status registerBibek Basu
Clear error status register during init Bug 1709814 Change-Id: I348526828015c84027b647bc728355ac9271a5fe Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/842868 Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-12-10ata: ahci: Enable 40 bit alignment detectionPreetham Chandru R
Bug 1694187 Change-Id: Idb8d95f0a7bc099989cc5b7b0bc97bf5cc896b32 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: http://git-master/r/837972 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2015-11-04video: tegra: host: Query vi/isp max clk-rateSudhir Vyas
Query max vi/isp clk-rate runtime to calcuate max BW. Remove max-bw defines. Bug 1538490 Bug 1695435 Change-Id: I86a5c22fa3c7c9582351bbe9a95776aaea6a613d Signed-off-by: Sudhir Vyas <svyas@nvidia.com> Reviewed-on: http://git-master/r/461278 (cherry picked from commit bbcd86c917430ceea1603e03964296ca4e26ac3a) Reviewed-on: http://git-master/r/825139 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jihoon Bang <jbang@nvidia.com> Tested-by: Frank Shi <fshi@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-10-29media: tegra_camera: introduce 2 kthreads for captureBryan Wu
Use one kthread to start capture a frame and wait for next frame start. Before waiting, it will move the current buffer to another queue which will be handled another kthread. The second kthread (capture_done) will wait for memory output done sync point event and handle the buffer to videobuffer2 framework as capture done. Bug 1686911 Change-Id: Ia092c708ecca3b2e7cbc657a96fd247ea4a00d2f Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/819177 GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-10-29media: tegra_camera: replace workqueue with kthreadBryan Wu
Use kthread instead of workqueue, which will create a dedicated kernel thread for capture. Remove useless mutex and convert spin_lock_irq() to normal spin_lock(). Bug 1686911 Change-Id: Ib236a7ebbdd0359f2705774a979825f1f9e9d82a Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/819176 GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-10-29media: tegra_camera: add line alignment checkBryan Wu
bytes_per_line should be 64 bytes aligned in Tegra. Add a function to check that and return the right value for LINE_STRIDE register. Bug 1694764 Change-Id: I1bb926a416719d19cad509f9a9a7c4fce06b851a Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/816975 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-10-14usb: gadget: composite: Fix cdev null after rmmodPeter Chiang
Avoid to disconnect gadget again after unbinding bug 200141741 Change-Id: I6fadcb4c5b5262d861a865f24ba2d8666e126923 Signed-off-by: Peter Chiang <pchiang@nvidia.com> Reviewed-on: http://git-master/r/805175 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Hui Fu <hfu@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
2015-09-28gpu: nvgpu: re-order POWERGATE_ENABLE operationsDeepak Nibade
re-order POWERGATE_ENABLE operations in opposite order of POWERGATE_DISABLE Bug 1679372 Change-Id: Ib72a0b80929e2dee2cf88a6d3d0f96d61c02307b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/796459 (cherry picked from commit 7e2668f924a986d4bd7d1d2c383431a5e80d9968) Reviewed-on: http://git-master/r/801977 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-09-28gpu: nvgpu: enable powergate always while releasing debug sessionDeepak Nibade
Currently, while releasing the debug session we enable powergate only if a channel is bound to session If a session has no channel bound to it, and has powergate disabled, then we do not enable powergate when that session is closed Fix this by calling dbg_set_powergate(POWERGATE_ENABLE) always while releasing the session Refcounting and sanity checks in dbg_set_powergate() will take care of situation if powergate was not disabled by the session in first place Bug 1679372 Change-Id: I4e027393c611d3e8ab4f20e195f31871086da736 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/796999 cherry picked from commit 671dff8cb0605f865c5da32bd889e2a6fcf133fe) Reviewed-on: http://git-master/r/801986 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-09-01Kernel: ar0330: change 720p settingsArun Kannan
Based on latest info from Aptina, change 720p settings. Bug 1643556 Change-Id: Ia1ea066ebf265670bb8e0503e9502ac9f24a27ff Signed-off-by: Arun Kannan <akannan@nvidia.com> Reviewed-on: http://git-master/r/748499 Reviewed-by: Winnie Hsu <whsu@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com>
2015-08-25video: tegra: dc: handle tegra_dc_sync_windows errorBibek Basu
In case tegra_dc_sync_windows is interrupted by signal, return the error to caller application Bug 200090492 Change-Id: Id69fbe38d0abe0b3e71eb5a413db241ebcf0a0ae Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/784754 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-08-19ax88179_178a: Correct the RX error definition in RX headerFreddy Xin
Correct the definition of AX_RXHDR_CRC_ERR and AX_RXHDR_DROP_ERR. They are BIT29 and BIT31 in pkt_hdr seperately. bug 200009821 Change-Id: Ib55e13899a68a86a847708500dccd475e2f0712a Signed-off-by: Freddy Xin <freddy@asix.com.tw> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: wtsai <wtsai@nvidia.com> Reviewed-on: http://git-master/r/434739 Reviewed-on: http://git-master/r/450229 (cherry picked from commit 67e4ec14734d8343116fe7a486de6ec0ad3b9e73) Reviewed-on: http://git-master/r/784056 GVS: Gerrit_Virtual_Submit Reviewed-by: ChihMin Cheng <ccheng@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
2015-08-07AR0330: validate with V4L2 for Jetson TK1Arun Kannan
Bug 1643556 Change-Id: I7330bd3ec33e2309577c75bac79e120167b0f81e Signed-off-by: Arun Kannan <akannan@nvidia.com> Reviewed-on: http://git-master/r/748395 Reviewed-by: Winnie Hsu <whsu@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com>
2015-08-05tegra: ictlr: decrease error severityBibek Basu
Don't panic in case of mselect error Bug 1652598 Change-Id: Ia07380dae0c10cdea24a865046e7f6bbec7389bc Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/778344 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2015-07-23arm: tegra: fix debug build issueBibek Basu
Initialize uninitialized variables to get the build through Bug 1640594 Change-Id: Ia0788c5852bb8d68a79004e3f2fa1b3d2b9ca2fe Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/772239 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-07-14backlight: pwm: Converting benign message to infoPankaj Dabade
Making message "unable to request PWM, trying legacy API". However, failure with legacy API will be treated as error. Bug 200113810 Change-Id: Ie7bae0c62837a4fde89706d1b9600600c2a49651 Signed-off-by: Pankaj Dabade <pdabade@nvidia.com> Reviewed-on: http://git-master/r/761732 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2015-06-24media:ar0330: add 4 lanes setting 2048x1296tegra-l4t-r21.4Ming Wong
bug 1655159 Change-Id: I5c09cb63075f3465e90aee4f3619df02c34bca95 Signed-off-by: Ming Wong <miwong@nvidia.com> Reviewed-on: http://git-master/r/757527 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2015-06-24mmc: tegra: reverify tuning best tapBibek Basu
tuning best_tap_value at times throws wrong value leading to data crc error. To make the SW robust, reverify tuning best_tap_value with previously calculated and then only proceed. Bug 200107220 Bug 200102727 Change-Id: If58194bcfd1f025b15f827b233b534b8fc999327 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/761054 GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Tested-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-19media: tegra_camera: add start streaming callBryan Wu
Queueing buffer might happen before starting streaming. So any queueing buffer operation before starting streaming shouldn't trigger real capture but just queue the buffer. After starting streaming, it will wake up kernel workqueue to start real capture. Bug 1639982 Change-Id: I66fd527bbd12790b2d688f320214976e70a658f3 Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/754710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-19media: tegra_camera: optimize single shot modeBryan Wu
Current single shot mode, pixel parser is disabled after capture one frame and software waits for memory write ack done syncpoint, which only gives us half the frame rate. Optimized single shot mode: - during capture setup, set single shot mode - for each frame, wait for FRAME_START syncpoint - arm single shot bit to start capture - for the last frame, wait for MWA_DONE syncpoint to make sure capture finished. With optimized single shot mode, frame rate is about 4208x3120 @ 24fps for IMX135 and 1920x1080 @ 30fps for AR0261. Bug 1639982 Change-Id: I0b15d02c2853647d03f5b2d38a7fe5c145174bd5 Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/754709 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-19Revert "video: tegra: Wait PMU finishes booting"Winnie Hsu
This reverts commit f69b7093accdacfa653b4bd45d78e04a2676dc2a. Bug 200055546 Bug 200114503 Change-Id: I165a3da9f418657d86bf39fbe3db2adc13762c87 Signed-off-by: Winnie Hsu <whsu@nvidia.com> Reviewed-on: http://git-master/r/759875
2015-06-18video: tegra: dsi: add delay after register writeNaveen Kumar S
Providing a small delay after writing to dc registers while stopping dc stream helps in stabilizing the registers. This helps in resolving the intermittent register read failure issue. bug 200087039 Change-Id: I159d1d75aa2472b9e33bc42d890382f33def218a Signed-off-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-on: http://git-master/r/746062 (cherry picked from commit d29669af88735a2aeeb87b26f8794c9bcbb9f058) Reviewed-on: http://git-master/r/756015 Reviewed-by: Pankaj Dabade <pdabade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2015-06-18Revert "mmc: tegra: Fix missing tap hole margins print"Jeetesh Burman
This reverts commit 6ad6591bf83670f91ab5f7628b5a6c3db3e9da4c. Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Change-Id: If31a8a2a53a804657ebc5878be8594230acba2aa Reviewed-on: http://git-master/r/759477 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-18Revert "mmc: tegra: disable card clk before setting tap"Jeetesh Burman
This reverts commit f9b36d3b89f76cc48678eeb7a27cb980e89901d0. Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Change-Id: Ie862afeda5e7e5b360775248fbbc49a031528a0b Reviewed-on: http://git-master/r/759476 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-18Revert "mmc: tegra: Use 100000 precision instead of 1000"Jeetesh Burman
This reverts commit 3c5f4d1060669ec73dc0ceb4e9a876a55a89c5eb. Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Change-Id: Ic0e3eb4bb892e69dbd808c1d55721290c561ac7c Reviewed-on: http://git-master/r/759475 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2015-06-18Revert "mmc: tegra: Initialize margin addition variables"Jeetesh Burman
This reverts commit af2031797899b32504e32af377fa65875c06a746. Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Change-Id: I21c89606f1eed0e7d4445c5dfcf7e6d2382829e7 Reviewed-on: http://git-master/r/759474 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-20 02:00:17 +0000