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and S24_LE formats"
This reverts commit be13ac391d27c925 ("MLK-15101: ASoC: imx-wm8962: Use a lower
FLL output rate for S20_3LE and S24_LE formats").
This breaks recording. We'll have to find a better fix for MLK-15101.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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S24_LE formats
Using a lower FLL out frequency seems to fix the sound distortion we hear
during playback of the second audio file from the command:
aplay -Dhw:0 -d 1 audio96k16b2c.wav audio96k24b2c.wav
Because the new frequency is half of the old one the existing BLCK compute
formula from wm8962 codec driver is still correct, it can derive the new
FLL output frequency.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 943149fc45dd937daafde6ab27f7cc5eb2b0cecb)
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Using a higher bitclk then expected doesn't always work.
Here is an example:
aplay -Dhw:0,0 -d 5 -r 48000 -f S24_LE -c 2 audio48k24b2c.wav
In this case, the required bitclk is 48000 * 24 * 2 = 2304000
but the closest bitclk that can be derived is 3072000.
Now, for format S24_LE, SAI will use slot_width = 24, but since
the clock is faster than expected, it will start to send bytes
from the next channel so the sound will be corrupted.
Thus, remove bitclk relaxation condition which was added mostly
for supporting S20_3LE format which was removed from SAI in
commit 739e6d654b5c0a ("MLK-14870: ASoC: fsl_sai: Remove support
for S20_3LE").
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Similar with 7c280619ed45b (" MLK-14663-2: ASoC: fsl: imx-wm8960: Kill
warning for non-gpr boards")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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This is similar with commit c79a82aec8ccf ("ASoC: fsl: imx-wm8960: Refactor
GPR parsing") and it is needed for easier adding support for non-gpr boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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A side effect of commit 5555277e693a7 ("MLK-13574-1: ASoC: imx-wm8960:
remove the gpr dependency") is that a warning was printed for boards
without gpr. This can be confusing.
imx7d boards do not have a gpr setting, so use imx7d-evk-wm8960
compatible string to avoid printing the warning.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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Refactor GPR handling into a function for easier adding support
for non-gpr boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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The maximum channel supported by sii902 is 2, but machine
driver use dummy codec, and there is no constraint list
from codec, so add constraint directly in machine driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Fix build error when SOC_IMX_PCM_DMA is not enabled
error: expected identifier or ‘(’ before ‘{’ token})
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 67ee27e3c97c8deb851ca61fab0e513009b93dbe)
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Dynamic constraints for supported sampling rates cannot prevent aplay to
play audio files with higher rates. So we remove the constraints and hard
reject the unsupported samples.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit f9f35e22e657845a593f6e3338e9e5acec6addc4)
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The ASRC support 24 bit input width, but for S20_3LE the input width
is 20 bit, asrc will treat it as 24bit, which like a 24bit data shift
4 bit right, the result is the volume is lower than expected.
ASRC can't shift the 20bit data left 4 bit internally, so remove the
S20_3LE in supported list, add S24_3LE in supported list.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Same as commit cfe36e2e7fce ("MLK-15043-2: ASoC: imx-cs42888: fix
noise issue with FE-BE case"). need to add same configuration
for imx-wm8960, imx-wm8962, imx-mqs.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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In master mode, clock of S20_3LE mono bistream is calculated by formula
"2 * params_width * params_rate", and this clock can't be divided from
clock soure, so switch to use the "2 * params_physical_width * params_rate"
formula to fix this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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The case is "aplay -Dhw:0,1 -d 5 -r 8000 -f S16_LE -c 9 audio8k16b9c.wav",
which is to playback 9 channel bitstream. But the maximum supported channel
of codec is 8, ALSA didn't return error for this case, but continue to
playback.
The reason is that in FE-BE case, ASLA only get the FE's hw parameter for
constraint list, omit the BE's parameter. This patch is to merge BE's
parameter to FE. in this situation with the 9 channel case, ASLA will
return error "aplay: set_params:1303: Channels count non available"
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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According to commit b073ed4e2126 ("ASoC: soc-pcm: DPCM cares BE format"),
Current DPCM only care FE channel, but it will set unsupported channel to
drivers.
So add dpcm_merged_chan, which is used to merge the BE's codec
channels configuration to FE if it exist in snd_soc_dai_link. And
dpcm_runtime_base_chan function is to get the channel configuration of BE,
which likes the dpcm_runtime_base_format function.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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There are boards without gpr setting, so it's better not to fail
in such cases and only print a warning.
This is related to commit ce72b6d2668049 ("MLK-13574-1: ASoC: imx-wm8960:
remove the gpr dependency").
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 882c373c74aecd27aad64062d4cceb89a4371c2e)
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The change introduced by commit 00c174b3b28a
("MLK-14525: ASoC: fsl_esai: channel swap issue in 3 channels or 5 channels")
is no longer valid after improvements added with commit c35bc6ae5c48
("MLK-14778: ASoC: fsl: imx-cs42888: Improve support for odd number of channels")
Because we use TDM instead of I2S for 3,5 and 7 channels we must
initialize ESAI with the actual number of channels. There is no need
to count the additional channel required when I2S was used.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 85a9aa0a73f80968445d8929f5ae9acb1972c8fe)
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with "echo 1 > /sys/class/graphics/fb0/blank", and there is no
usb connected on board, the system may enter low power mode,
then audio playback will be failed. use pm_qos to prevent A7
core enter low power mode during audio playback and recording.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit ea80731e828695bcfbf0d20c966813c3bdddfb88)
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samples
When starting a playback the initialization data used to reduce underruns
was send to the transmit data register after the DMA requests were enabled.
This patch moves the initialization phase before enabling the DMA so the
data is transmitted in correct order.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
(cherry picked from commit 44e5c11332390a8b1c09d33d5653cb6673e9eea4)
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For samples with more than 2 and odd number of channels the I2S mode
does not work correctly. In I2S mode we are required to activate an even
number of channels (possibly on multiple datalines) and thus configure
the BCLK for even channels. In this case samples with odd (smaller) number
of channels are played faster and the sound is distorted.
To fix this behavior we can enable TDM mode for the special cases of
samples with 3, 5 or 7 channels. But even TDM has some restrictions that
prevent us from having full support for the special cases:
1. TDM is not supported by codec in master mode so 3, 5 and 7 channels
usage is denied.
2. In codec slave mode TDM works only with 8 slots and slot width of 32
bits. For an often used MCLK frequency of 24MHz and the above restrictions
the maximum sample rate is limited to 48KHz = 24576000/(2*8*32).
The 2 denominator is required by ESAI BCLK divisors.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
(cherry picked from commit c35bc6ae5c48f62bae534ce8d2d818f857778ff8)
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With current clock configuration we cannot derive bitclk for S20_3LE
format in SAI master mode. There was an attempt to fix this in commit
65e6b5f1b4a7 ("MLK-14536: ASoC: wm8960: Fix playback in CPU DAI master mode")
but this broke codec-master mode, thus the patch was partially reverted in
96f0d36e420 ("MLK-14798: arm: dts: imx6ul: Fix wm8960 codec master mode")
So, remove S20_3LE support for SAI master mode. Clients using this
feature should use codec master mode, which is the default one in the
dts anyway.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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There is error log "wm8962 3-001a: Unsupported BCLK ratio 6"
When the bitstream's format is S20_3LE.
The reason is that the pll output is samplerate*256, which
can't divide to clock samplerate*20*2. So in this patch change
the pll output to samplerate*384, and use the physical_width
for S20_3LE to calculate the bclk.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
SAI master mode")
This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
set xCR4/xCR5/xMR for SAI master mode") from upstream.
Manually adjust the code to match the changes introduced by subsequent
commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
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Commit 665ced16cf044 ("MLK-10050 dma: imx-sdma: add support for sdma
memory copy") enforces maximum SDMA buffer descriptor length at 65532,
but doesn't update period_bytes_max or max_segment size in DMA drivers.
Thus, resulting in the following bug:
$ arecord -Dhw:0,0 -r 192000 -f S20_3LE -c 1 -d 10 audio192k20b1c.wav
imx-sdma: SDMA channel 5: maximum period size exceeded: 65534 > 65532
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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which don't request the dma channel in the probe, but request
dma channel when needed. for the dma channel of cpu dai in BE
can be reused by the FE.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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Set specific fmt for emulation build, for i2s xtor receiver is
in slave mode and i2s xtor transmitter is in master mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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The SAI interface can be a clock supplier or consummer
as function of stream direction, ie when interacting
with I2S XTOR. Removed FSL_SAI_RFR define as it is now
referred as FSL_SAI_RFR0.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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sai can support 32 channel in maximum.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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SAI & ESAI interfaces may share the same interrupt with EDMA,
so that we need a flag to trigger proper shared interrupt
handling. For compatibility the same DT flag, "shared-interrupt",
is introduced as the one used in drivers/dma/fsl-edma-v3.c.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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The ESAI_xCR_xWA is xCR's bit, not the xCCR's bit. driver set it to
wrong register, correct it in this patch.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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In ESAI synchronous mode, the clock is generated by Tx, So
we should always set registers of Tx which relate with the
bit clock and frame clock generation (TCCR, TCR, ECR), even
there is only Rx is working.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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The case is 32kHz/24bit/1channel bit stream, and ssi is in master mode.
The driver will switch to normal mode for 1 channel, so the slot width
is not fixed to 32 bit in this mode, and even in mono mode, the slot
number is 2, but the bit clock calulation still use the bit width=32,
and slot number=1, which cause the output frameclock is not correct.
So there will be noise in output sound.
This patch is to change the bit clock formula of mono mode, which is
2channels * params_width * sample rate.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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Add I2S XTOR machine driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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With the current rates for MCLK is not possible to derive bitclk
for all files in S20_3LE format and also for files with S24_LE sampled
at 48000Hz.
In order to fix this, we need to find a better MCLK value. We did this
in two steps:
1) Use params_physical_width to get rid of S20_3LE burden.
2) Brute force into all available rates which can pass fsl_sai_set_bclk
algorithm.
Thus we found 36864000 to be the smallest acceptable rate for MCLK.
Reviewed-by: Mihai Serban <mihai.serban@nxp.com>
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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Add common imx_stop_lock_pcm_streams and imx_start_unlock_pcm_streams
functions to remove code duplication in fsl_asrc and fsl_esai.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
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The pulse audio will set a wrong buffer size which is not the integral
multiple of period size, it will cause the DMA can't work correctly in
M4 side.
The reason is that we always need to add a constraint for
SNDRV_PCM_HW_PARAM_PERIODS, which make it integer.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 54a10a6c2130a69aca4c1923dac3a15137911146)
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Capture and Playback work in parallel in master mode, stop one substream,
the other substream will be conflicted, for clock is disabled.
The reason is that the clock counter is not increased in second substream,
the hw_param() function returned in the beginning for first substream is
enabled.
This patch is to move the clock enablement before the device enablement
checking in hw_param().
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Fixes: 95461157dea0 ("MLK-14316 ASoC: fsl_ssi: Fix playback and capture
with mono stream")
This commit (95461157dea0) cause a side effect for i2s mode, for it clears
the setting of I2S_MODE, the basic idea is the set_fmt() function should
not touch the I2S_MODE and NET mode of SCR.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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RTOS for M4 core in imx7ulp don't support 32kHz and 44kHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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In suspend and resume, the M4 side will reset hw parameter for tx
and rx, when only tx is working, the parameter of rx is a old value,
which will cause the parameter is not sync with tx and rx.
currently the M4 audio can only work in sync mode, so set both
parameter in same time.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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The test case is to playback a bitstream, then repeat ctrl+z and fg,
several times later, the playback is failed to continue.
The reason is if the work is pending in work queue, send second time
of this work, the second work is dropped by work queue. so use one
work for one cmd is not fit for audio case. use a work loop for audio
cmd to fix this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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fsl_asrc_reset can be called from interrupt context with interrupts
disabled via sdma_int_handler -> imx_pcm_dma_complete. In this case we
need to make sure we don't reenable interrupts.
However, start_unlock_stream uses the _irq version of
snd_pcm_stream_unlock which means that interrupts will be enabled at
the end of that function.
This patch switches to the _irqsave/_irqrestore version of
snd_cpm_stream_lock/unlock to avoid the above issue and fix the
following warning:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at kernel/irq/handle.c:151 __handle_irq_event_percpu+0x150/0x154
irq 61 handler sdma_int_handler+0x0/0x34c enabled interrupts
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.11-02052-g4c94f9e-dirty #684
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[<8010ed08>] (unwind_backtrace) from [<8010b350>] (show_stack+0x10/0x14)
[<8010b350>] (show_stack) from [<803bae4c>] (dump_stack+0x88/0x9c)
[<803bae4c>] (dump_stack) from [<8012d82c>] (__warn+0xe8/0x100)
[<8012d82c>] (__warn) from [<8012d87c>] (warn_slowpath_fmt+0x38/0x48)
[<8012d87c>] (warn_slowpath_fmt) from [<80170a48>] (__handle_irq_event_percpu+0x150/0x154)
[<80170a48>] (__handle_irq_event_percpu) from [<80170a68>] (handle_irq_event_percpu+0x1c/0x58)
[<80170a68>] (handle_irq_event_percpu) from [<80170adc>] (handle_irq_event+0x38/0x5c)
[<80170adc>] (handle_irq_event) from [<80173e3c>] (handle_fasteoi_irq+0xd0/0x1a8)
[<80173e3c>] (handle_fasteoi_irq) from [<8016fc78>] (generic_handle_irq+0x24/0x34)
[<8016fc78>] (generic_handle_irq) from [<80170194>] (__handle_domain_irq+0x7c/0xec)
[<80170194>] (__handle_domain_irq) from [<801014c4>] (gic_handle_irq+0x48/0x8c)
[<801014c4>] (gic_handle_irq) from [<8010be8c>] (__irq_svc+0x6c/0xa8)
Exception stack(0x80f01f20 to 0x80f01f68)
1f20: 00000000 00000002 00000001 f4a00600 00000001 daf1ce68 4f334151 00000014
1f40: 4ef44986 00000014 00000004 80f03144 8010e30c 80f01f70 80999fb8 806c8808
1f60: 200f0013 ffffffff
[<8010be8c>] (__irq_svc) from [<806c8808>] (cpuidle_enter_state+0xec/0x264)
[<806c8808>] (cpuidle_enter_state) from [<80166e4c>] (cpu_startup_entry+0x148/0x21c)
[<80166e4c>] (cpu_startup_entry) from [<80e00c58>] (start_kernel+0x37c/0x388)
---[ end trace c7e4dec8204cf86b ]---
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
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In 3 channels, ESAI is set to I2S mode and two dataline, so actually
ESAI is working in 4 channels mode, (we can't get correct 3 channels,
for we can't make one dataline working in 2 channel, another dataline
working in 1 channels).
In this case, we fill channels (3) zero data to FIFO in start phase,
which should cause channel swap, that we need to fill 4 zero data to
FIFO for ESAI working in 4 channels mode actually.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add warning message for both divider of input clock and output clock
exceed the maximum value. which is useful for debugging.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Bitclk is derived from sysclk using bclk_divs.
Sysclk can be derived in two ways:
(1) directly from MLCK
(2) MCLK via PLL
Commit 3c01b9ee2ab9d0d ("ASoC: codec: wm8960: Relax bit clock
computation")
relaxed bitclk computation when sysclk is directly derived from MCLK.
Lets do the same thing when sysclk is derived via PLL.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
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Add a separate function for deriving (sysclk, lrclk, bclk)
when the clock is auto or pll.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
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WM8960 derives bit clock from sysclock using BCLKDIV[3:0] of R8
clocking register (See WM8960 datasheet, page 71).
There are use cases, like this:
aplay -Dhw:0,0 -r 48000 -c 1 -f S20_3LE -t raw audio48k20b_3LE1c.pcm
where no BCLKDIV applied to sysclock can give us the exact requested
bitclk, so driver fails to configure clocking and aplay fails to run.
Fix this by relaxing bitclk computation, so that when no exact value
can be derived from sysclk pick the closest value greater than
expected bitclk.
Suggested-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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Add a separate function for finding (sysclk, lrclk, bclk)
when the clock is auto or mclk. This makes code easier to
read and reduces the indentation level in wm8960_configure_clocking.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
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After starting playback with a single channel SSI runs in Normal mode
(SCR.net = 0b, SCR.i2s_mode = 00b). But, if starting also capture
in parallel with playback the SSI mode changes which breaks the playback.
This happens because, we can change SSI mode from two distinct places:
* _fsl_ssi_set_dai_fmt
* fsl_ssi_hw_params
When running playback and capture in parallel for a mono channel, changing
hw params for the second stream will have no effect.
This patch allows changing the mode only from fsl_ssi_hw_parms so that
we have an atomic view of SSI mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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Currently the M4 audio driver don't support mono channel, so remove it.
After mono channel is supported in M4 os, this commit should be reverted.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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