From 4ae8208660f838a7e31bdc1691026dada2920126 Mon Sep 17 00:00:00 2001 From: Heechul Yun Date: Mon, 11 Jul 2011 18:12:38 -0700 Subject: ARM: remove unnecesarry L2 cache flush The memory barrier, mb(), flush L2 cache which is unnecessary for bit operations because D cache is coherent for all CPUs This patch improves scalability of the system. Change-Id: I3bec7ec767849091b6da720869241f3a16a7b5cb Reviewed-on: http://git-master/r/40504 Reviewed-by: Yu-Huan Hsu Tested-by: Heechul Yun Reviewed-by: Heechul Yun Reviewed-by: Scott Williams --- arch/arm/include/asm/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 338ff19ae447..ee3bf9a7df1f 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -26,8 +26,8 @@ #include #include -#define smp_mb__before_clear_bit() mb() -#define smp_mb__after_clear_bit() mb() +#define smp_mb__before_clear_bit() smp_mb() +#define smp_mb__after_clear_bit() smp_mb() /* * These functions are the basis of our bit ops. -- cgit v1.2.3