From 763f2ee657b24124d7a0b561b61bdb26231b0169 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 24 May 2010 14:58:13 -0700 Subject: Revert "parisc: Set PCI CLS early in boot." This reverts the following patch, which shouldn't have been applied to the .32 stable tree as it causes problems. commit 5fd4514bb351b5ecb0da3692fff70741e5ed200c upstream. Set the PCI CLS early in the boot process to prevent device failures. In pcibios_set_master use the new pci_cache_line_size instead of a hard-coded value. Signed-off-by: Carlos O'Donell Reviewed-by: Grant Grundler Signed-off-by: Kyle McMartin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/pci.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c index 9e74bfe071dc..f7064abc3bb6 100644 --- a/arch/parisc/kernel/pci.c +++ b/arch/parisc/kernel/pci.c @@ -18,6 +18,7 @@ #include #include +#include /* for L1_CACHE_BYTES */ #include #define DEBUG_RESOURCES 0 @@ -122,10 +123,6 @@ static int __init pcibios_init(void) } else { printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); } - - /* Set the CLS for PCI as early as possible. */ - pci_cache_line_size = pci_dfl_cache_line_size; - return 0; } @@ -174,7 +171,7 @@ void pcibios_set_master(struct pci_dev *dev) ** upper byte is PCI_LATENCY_TIMER. */ pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, - (0x80 << 8) | pci_cache_line_size); + (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); } -- cgit v1.2.3