From 8b01df53dc6d9e8ea78cfe287678304e73d4bc9e Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Sat, 13 Feb 2010 22:46:56 -0800 Subject: tegra RM: Moved EMC DFS low corner to 18MHz. Moved EMC DFS low corner from 50MHz to 18MHz (affects LPDDR2 platforms). It is possible now, since EMC BCT configuration bug 632015 is fixed. Change-Id: I3a5bc3ebb7fb5fac1e70327970b6a215152d1cab --- arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h index 0f104fe2ae02..36338f89d122 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h @@ -190,7 +190,7 @@ extern "C" */ #define NVRM_DFS_PARAM_EMC_AP20 \ NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \ - 50000, /* Minimum domain frequency 50 MHz */ \ + 18000, /* Minimum domain frequency 18 MHz */ \ 1000, /* Frequency change upper band 1 MHz */ \ 1000, /* Frequency change lower band 1 MHz */ \ { /* RT starvation control parameters */ \ -- cgit v1.2.3