From aaae1b3660d8d1c6f0cfe2aeeb510b395a303d44 Mon Sep 17 00:00:00 2001 From: Scott Williams Date: Tue, 21 Feb 2012 17:20:10 -0800 Subject: ARM: tegra: Do not unlock CoreSight register access There is no reason to unlock APB CoreSight register access in the kernel. The debugger can perform it's own unlock operation as needed. Keep the registers write-protected to prevent inadvertent access. Change-Id: I22f28f76b5dd498b3782ab3380a04f865b59d6fd Signed-off-by: Scott Williams Reviewed-on: http://git-master/r/85039 Reviewed-by: Aleksandr Frid Reviewed-by: Krishna Reddy Reviewed-by: Bo Yan --- arch/arm/mach-tegra/headsmp.S | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4763528a5f16..5bb68433050a 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -49,7 +49,6 @@ */ ENTRY(tegra_secondary_startup) bl tegra_invalidate_l1 - bl tegra_enable_coresite b secondary_startup ENDPROC(tegra_secondary_startup) #endif @@ -63,7 +62,6 @@ ENDPROC(tegra_secondary_startup) * re-enabling sdram. */ ENTRY(tegra_resume) - bl tegra_enable_coresite bl tegra_invalidate_l1 cpu_id r0 @@ -134,12 +132,6 @@ tegra_invalidate_l1: isb mov pc, lr - /* Enable Coresight access on cpu */ -tegra_enable_coresite: - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 - mov pc, lr - /* * __tegra_cpu_reset_handler_halt_failed: * @@ -172,8 +164,6 @@ ENTRY(__tegra_cpu_reset_handler_start) ENTRY(__tegra_cpu_reset_handler) #if DEBUG_CPU_RESET_HANDLER - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 @ Enable CoreSight access b . #endif #ifndef CONFIG_TRUSTED_FOUNDATIONS -- cgit v1.2.3