From c830be18de92cf690e66a5dea9a725a8467c62b6 Mon Sep 17 00:00:00 2001 From: Scott Williams Date: Thu, 26 May 2011 13:20:13 -0700 Subject: arm: tegra: Change Tegra3 L2 cache prefetch to next line Change L2 cache prefetch offset from 8th line to next line. Change-Id: Ie88008e2ab5a882235ae91d71d193e898ca67121 Reviewed-on: http://git-master/r/33195 Reviewed-by: Niket Sirsi Tested-by: Niket Sirsi --- arch/arm/mach-tegra/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 5e4856b26e2b..2655d45efbb2 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -161,7 +161,7 @@ void __init tegra_init_cache(void) #endif /* Enable PL310 double line fill feature. */ - writel(((1<<30) | 7), p + L2X0_PREFETCH_OFFSET); + writel(((1<<30) | 0), p + L2X0_PREFETCH_OFFSET); #endif aux_ctrl = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (aux_ctrl & 0x700) << (17-8); -- cgit v1.2.3