From d2a1d360abc87215e6474334bdf395800b732020 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 18 Nov 2011 22:46:04 -0800 Subject: ARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltage Updated Tegra3 xL core speedo and nominal voltage settings. Re-factored nominal voltage selection, since new data introduced dependency of core voltage on both CPU and core speedo id. Bug 841336 Signed-off-by: Alex Frid (cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675) (cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301) Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1 Reviewed-on: http://git-master/r/67014 Reviewed-by: Diwakar Tundlam Tested-by: Aleksandr Frid Reviewed-by: Yu-Huan Hsu Rebase-Id: Rd35cb9ac1fbcb424548e05d10d5622744394e796 --- arch/arm/mach-tegra/fuse.h | 4 ++++ arch/arm/mach-tegra/tegra3_dvfs.c | 17 +++------------- arch/arm/mach-tegra/tegra3_speedo.c | 39 +++++++++++++++++++++++++++++++++---- 3 files changed, 42 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index bf3d7240863a..7b76ee54b78c 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -36,6 +36,8 @@ int tegra_cpu_process_id(void); int tegra_core_process_id(void); int tegra_cpu_speedo_id(void); int tegra_soc_speedo_id(void); +int tegra_cpu_speedo_mv(void); +int tegra_core_speedo_mv(void); void tegra_init_speedo_data(void); #ifndef CONFIG_ARCH_TEGRA_2x_SOC @@ -50,6 +52,8 @@ static inline int tegra_cpu_process_id(void) { return 0; } static inline int tegra_core_process_id(void) { return 0; } static inline int tegra_cpu_speedo_id(void) { return 0; } static inline int tegra_soc_speedo_id(void) { return 0; } +static inline int tegra_cpu_speedo_mv(void) { return 1000; } +static inline int tegra_core_speedo_mv(void) { return 1200; } static inline void tegra_init_speedo_data(void) { } #endif diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index de961f935b4e..4ec22d1b9485 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -37,14 +37,6 @@ static const int cpu_millivolts[MAX_DVFS_FREQS] = static const int core_millivolts[MAX_DVFS_FREQS] = {1000, 1050, 1100, 1150, 1200, 1250, 1300}; -static const int core_speedo_nominal_millivolts[] = -/* speedo_id 0, 1, 2 */ - { 1200, 1200, 1300 }; - -static const int cpu_speedo_nominal_millivolts[] = -/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8 */ - { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150 }; - #define KHZ 1000 #define MHZ 1000000 @@ -425,7 +417,6 @@ static int __init get_cpu_nominal_mv_index( * nominal core voltage ("solve from cpu to core at nominal"). Clip * result to the nominal cpu level for the chips with this speedo_id. */ - BUG_ON(speedo_id >= ARRAY_SIZE(cpu_speedo_nominal_millivolts)); mv = tegra3_dvfs_rail_vdd_core.nominal_millivolts; for (i = 0; i < MAX_DVFS_FREQS; i++) { if ((cpu_millivolts[i] == 0) || @@ -435,7 +426,7 @@ static int __init get_cpu_nominal_mv_index( BUG_ON(i == 0); mv = cpu_millivolts[i - 1]; BUG_ON(mv < tegra3_dvfs_rail_vdd_cpu.min_millivolts); - mv = min(mv, cpu_speedo_nominal_millivolts[speedo_id]); + mv = min(mv, tegra_cpu_speedo_mv()); /* * Find matching cpu dvfs entry, and use it to determine index to the @@ -479,7 +470,8 @@ static int __init get_cpu_nominal_mv_index( static int __init get_core_nominal_mv_index(int speedo_id) { - int i, mv; + int i; + int mv = tegra_core_speedo_mv(); int core_edp_limit = get_core_edp(); /* @@ -487,9 +479,6 @@ static int __init get_core_nominal_mv_index(int speedo_id) * make sure core nominal voltage is below edp limit for the board * (if edp limit is set). */ - BUG_ON(speedo_id >= ARRAY_SIZE(core_speedo_nominal_millivolts)); - mv = core_speedo_nominal_millivolts[speedo_id]; - if (core_edp_limit) mv = min(mv, core_edp_limit); diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index a0307ba33682..5c37fd3f3a84 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -52,8 +52,8 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { {192}, /* [9]: soc_speedo_id = 2 - T33S */ /* T30 'L' family */ - {192}, /* [10]: soc_speedo_id 2: T30L */ - {192}, /* [11]: soc_speedo_id 2: T30SL */ + {192}, /* [10]: soc_speedo_id 1: T30L */ + {192}, /* [11]: soc_speedo_id 1: T30SL */ }; /* Maximum speedo levels for each CPU process corner */ @@ -170,7 +170,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) switch (package_id) { case 1: /* MID => T30L */ cpu_speedo_id = 7; - soc_speedo_id = 2; + soc_speedo_id = 1; threshold_index = 10; break; case 2: /* DSC => T30S */ @@ -188,7 +188,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) case 0x8F: /* T30SL */ cpu_speedo_id = 8; - soc_speedo_id = 2; + soc_speedo_id = 1; threshold_index = 11; break; @@ -340,3 +340,34 @@ int tegra_package_id(void) { return package_id; } + +/* + * CPU and core nominal voltage levels as determined by chip SKU and speedo + * (not final - can be lowered by dvfs tables and rail dependencies; the + * latter is resolved by the dvfs code) + */ +static const int cpu_speedo_nominal_millivolts[] = +/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8 */ + { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150 }; + +int tegra_cpu_speedo_mv(void) +{ + BUG_ON(cpu_speedo_id >= ARRAY_SIZE(cpu_speedo_nominal_millivolts)); + return cpu_speedo_nominal_millivolts[cpu_speedo_id]; +} + +int tegra_core_speedo_mv(void) +{ + switch (soc_speedo_id) { + case 0: + return 1200; + case 1: + if ((cpu_speedo_id != 7) && (cpu_speedo_id != 8)) + return 1200; + /* fall thru for T30L or T30SL */ + case 2: + return 1300; + default: + BUG(); + } +} -- cgit v1.2.3