From f897161f10aae5b86656e05cb4c5a1541d71540a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 31 Oct 2018 12:38:07 +0100 Subject: apalis-imx8qm: enable sata Add external clock nodes to model the on-module SATA reference clock generator. Assign it to the SATA instance so it can be disabled if required. Signed-off-by: Marcel Ziswiler (cherry picked from commit 73e0d2dcb1326fb64ddb7cadb5ca211b058f39ba) While forward poriting, add newly required phy_apbclk to the clocks property. Signed-off-by: Max Krummenacher --- arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 75c39e765472..c7db6d2609f5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -953,6 +953,21 @@ status = "okay"; }; +&sata { + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>, + <&pcie_sata_refclk_gate>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "phy_apbclk", "sata_ext"; + status = "okay"; +}; + &ldb2_phy { status = "okay"; }; -- cgit v1.2.3