From c8f5a878e55459b78bac273f6492bbc91475beb5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 11 Jun 2015 13:51:12 +0200 Subject: ARM: mvebu: use DT properties to fine-tune the L2 configuration In order to optimize the L2 cache performance, this commit adjusts the configuration of the L2 on the Cortex-A9 based Marvell EBU processors (Armada 375, 38x and 39x), using the appropriate DT properties. We enable double linefill, incr double linefill, data prefetch and disable double linefill on wrap. This matches the configuration that was fine tuned in the Marvell BSP. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts/armada-39x.dtsi') diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 619b79043eee..dc6efd386dbc 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -104,6 +104,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu@c000 { -- cgit v1.2.3