From b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 16 Feb 2017 21:50:40 +1300 Subject: ARM: dts: mvebu: Move mv98dx3236 clock bindings Previously the coreclk binding for the 98dx3236 SoC was inherited from the armada-370/xp. This block is present in as much as it is possible to read from the register location without causing any harm. However the actual sampled at reset values are reflected in the DFX block. Moving the binding to the DFX block enables support for different clock strapping options in hardware. Signed-off-by: Chris Packham Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts/armada-xp-98dx3236.dtsi') diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 5e7245524d46..3f3ec9e1f8af 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -176,18 +176,12 @@ }; gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; + compatible = "marvell,mv98dx3236-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; - coreclk: mvebu-sar@18230 { - compatible = "marvell,mv98dx3236-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,mv98dx3236-cpu-clock"; @@ -264,6 +258,12 @@ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; reg = ; + coreclk: mvebu-sar@f8204 { + compatible = "marvell,mv98dx3236-core-clock"; + reg = <0xf8204 0x4>; + #clock-cells = <1>; + }; + dfx_coredivclk: corediv-clock@f8268 { compatible = "marvell,mv98dx3236-corediv-clock"; reg = <0xf8268 0xc>; -- cgit v1.2.3