From b5584b2bc2038ab4b7051c97ae2351ef83d193f4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 6 Jun 2013 11:21:23 +0200 Subject: arm: mvebu: armada-xp-db: ensure PCIe range is specified The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-db.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/armada-xp-db.dts') diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index f5fc1a3868a2..e28e68ff864d 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -31,6 +31,7 @@ soc { ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ internal-regs { -- cgit v1.2.3